Multi-NoC SoC Performance Analysis and Architectural Exploration for Time Sensitive Networking (TSN) Applications

FPGA's are pervasive everywhere, even more so in industrial and embedded domains requiring support for diverse workloads with low latency requirements. In order to provide flexibility of programmable logic with power and cost savings of hard IP, a hard processor system along with FPGA fabric delivers reduced board space, system power and TCO savings by eliminating a discrete embedded processor. 

This presentation will cover architectural exploration and performance modeling for Time Sensitive Networking (TSN) applications using Synopsys Platform Architect. Extensive design space exploration and system performance analysis was done with multiple NoC’s, peripherals and memory hierarchy that enabled left shift architectural optimization and sign off 8 months ahead of RTL.