Optimizing SoC Performance for Networking Workloads: Fabric, System Cache, and DRAM

Optimizing the performance of System-on-Chip (SoC) designs requires a comprehensive understanding of the workload characteristics and complex interactions between fabric interconnects, system caches, and DRAM controllers. In this presentation we will share a robust methodology to model different workloads and orchestrate design space exploration (DSE) for performance optimization of these critical SoC components using Synopsys Platform Architect.

Intel’s approach utilizes the advanced capabilities of Synopsys Platform Architect to create detailed and accurate workload models and use performance models of the fabric, system cache, and DRAM controller. By integrating these models with heuristic optimization techniques, we conduct an efficient and exhaustive exploration of the design space, identifying configurations that offer the best trade-offs between performance, power, and area (PPA). We specifically address the challenges posed by multi-agent Core-IO traffic, focusing on the intricate interactions between compute and memory subsystems.

The results demonstrate marked improvements in design efficiency, with optimized configurations achieving orders of improvement in Performance compared to baseline designs. This methodology equips industry practitioners with a powerful tool set for early-stage SoC DSE, enabling more informed design decisions and enhancing the overall performance of computing systems.