Interconnect and Memory Performance Exploration of Many-Core SoCs

Early validation of system architecture decisions is crucial to avoid delays and meet product requirements. Kalray's ManyCore chips, designed for storage, compute and AI applications, need high compute efficiency and optimized dataflows between the chip's interfaces, main memory, and local memory. The efficiency of these dataflows depends on various hardware and software parameters, such as workload patterns, the number of concurrent workloads, DRAM transaction distribution, DRAM scheduling policies, and interconnect configurations.

Using Synopsys Platform Architect, with generic IP and Arm performance models, we created a performance SystemC simulation platform that helps validate architectural assumptions early on, guiding data-driven decisions during chip design. Kalray’s simulation platform, which can be quickly developed without needing RTL availability, supports continuous integration to detect potential architecture regressions. Kalray plans to enhance the model's accuracy by integrating IP models as the design progresses.