Software-Enabled Full Chip Power Signoff & SoC Verification

Godwin Maben

Nov 03, 2021 / 5 min read

Understanding Your Power Consumption in the Real World

In the real world, the demand for AI chips is driving the trend towards bigger, smarter, and faster SoC designs. Consequently, low-power design, analysis, verification, and power signoff challenges are not getting any easier, as chip designs deploy increasingly smaller geometries that dissipate more and more power. Despite this dilemma, the quest for further power reductions continues apace.

To address this challenge, low-power verification, power analysis, and power signoff must start from the system level and MUST involve running realistic software workloads. The complexity of software driving the hardware is such that it has become a key determinant of how the design is taxed in terms of power characteristics (that provoke power-related bugs). Real-world software ensures the design is tested with meaningful and long enough sequences to find these bugs. Emulation is the technology that can scale to meet the size of these designs, run at fast enough speeds, and allow the use of real-world software loads.

Having established the MUST-have plan for low-power verification, you then need to consider a plan for power signoff which will ensure a high degree of confidence, using emulation.

Software-driven power verification drives more efficient signoff

In the recent blog Empowered By Real-World Software to Find Power Bugs, we talked about how the Synopsys ZeBu® Empower emulation system enables verification teams to exploit realistic software payloads when analyzing the power characteristics of their SoC hardware. In this blog, we will explore the challenges of full chip-level power signoff using ZeBu Empower in more detail.

The Limitations of Full Chip Power Signoff with Simulation

The challenge with performing full chip power signoff using simulation is in choosing the right simulation cycles for signoff. Say you have the most capable tools. How do you then determine that the chosen simulation cycles are the ones that best represent typical average and peak power consumption for the design?

You can make an educated guess… but…

Your existing simulation tests are not necessarily fit for purpose when it comes to power analysis, even though you may have a lot of them. Using directed unit-level tests on individual blocks may not resemble the real-world application of this IP in the SoC context. Therefore, you may decide to create new test cases targeted at high power consumption scenarios. In these cases, you will focus on achieving the highest possible activity levels by enabling the maximum number of functions to be operating with the highest possible traffic levels and maximum number of power domains active. This is your max-power workload.

Alternatively, you might choose a standard benchmark like Dhrystone and run sections of that under the conditions of an “all-on” setup for the design. In other words, turn on all the lights and all the appliances and then go check the electricity meter!

How confident are you that you have realistically configured your design and have loaded a realistic workload?

If you are going to all the trouble of running power vectors on back-annotated timing netlist simulations for accurate power signoff, this fidelity of measurement could be pointless if you have chosen inappropriate power vectors. Is it close enough to the actual power consumption of a real system running real software payloads under realistic loading conditions? You might be missing a real scenario that will be encountered in the final silicon when running the target software. Then you have a power bug!

You Need to Run Realistic Software Payloads

So, simulation power signoff may point you to some power issues, but it might not represent the reality of running the target system and, hence, you may likely miss important power bugs. We know that we must functionally validate our designs using the target or at least realistic software, and we know that the best way to do this in a practical timeframe is with emulation or FPGA prototyping. Both allow you to run fast enough to boot the operating system and run real application code. If you can start power analysis and power signoff in an environment such as this, you can be more confident that you are signing-off power with truly representative cycles and operating conditions.

Synopsys ZeBu® Empower emulation system is the most capable and highest performing emulation system to enable software-driven power analysis and power signoff. The system delivers breakthrough performance for fast hardware-software power verification. Its performance enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. The power profiles can be used by software and hardware designers to identify substantial power improvement opportunities for dynamic and leakage power much earlier. The ZeBu Empower solution also feeds forward power-critical blocks and time windows into the Synopsys PrimePower® power signoff solution to accelerate RTL power analysis and gate-level power signoff.

Finding the Right Signoff Windows

The challenge is to find the best power windows of interest from within billions of cycles of activity, then run your fully back-annotated power signoff using the PrimePower engine. The ZeBu Empower system facilitates this with a flow that allows you to start from the top – billions of cycles of activity, and then zoom in to smaller power windows of interest where full power signoff can be conducted.

This progressive zoom-in allows you to visualize where the areas of high activity are across the entire software execution timeframe, typically billions of cycles, with sufficient accuracy that smaller power windows of millions of cycles can be accurately identified. The ZeBu Empower solution then enables you to zoom into these smaller power windows and perform more accurate power analysis to determine peak power and average power consumption, and to further identify even smaller power windows of interest (thousands of cycles) which can be selected for power signoff.

Power Activity Cycles Chart | Synopsys

This provides an ability to increase the fidelity of the analysis by performing the power analysis using RTL, post-synthesis netlists, and post place-and-route netlists. Post place-and-route analysis should be able to consume real timing data (SDF), real RC parasitic data (SPEF), and technology library data (.lib)) and achieve full-accuracy power signoff using the PrimePower solution. During implementation and signoff, the signoff solution provides accurate gate-level power analysis reports for SoC designers to make timely design optimizations and meet power targets. Supported power analysis includes average power, peak power, glitch power, clock network power, dynamic and leakage power, and multi-rail power; with activity from RTL and gate-level simulation, emulation, and vectorless analysis. By closely integrating with the Synopsys PrimeTime® golden industry standard timing and signal integrity analysis and signoff solution, PrimePower technology expands the PrimeTime solution to deliver accurate dynamic and leakage power analysis and signoff for gate-level designs.


We’ve been talking about power signoff in the context of full chip level. Power aware emulation in the form of the ZeBu Empower system, in combination with the PrimePower solution, is the fastest path to full chip power signoff based on the power characteristics of executing system-realistic software with system-realistic activity levels.

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