In the real world, the demand for AI chips is driving the trend towards bigger, smarter, and faster SoC designs. Consequently, low-power design, analysis, verification, and power signoff challenges are not getting any easier, as chip designs deploy increasingly smaller geometries that dissipate more and more power. Despite this dilemma, the quest for further power reductions continues apace.
To address this challenge, low-power verification, power analysis, and power signoff must start from the system level and MUST involve running realistic software workloads. The complexity of software driving the hardware is such that it has become a key determinant of how the design is taxed in terms of power characteristics (that provoke power-related bugs). Real-world software ensures the design is tested with meaningful and long enough sequences to find these bugs. Emulation is the technology that can scale to meet the size of these designs, run at fast enough speeds, and allow the use of real-world software loads.
Having established the MUST-have plan for low-power verification, you then need to consider a plan for power signoff which will ensure a high degree of confidence, using emulation.
Software-driven power verification drives more efficient signoff
In the recent blog Empowered By Real-World Software to Find Power Bugs, we talked about how the Synopsys ZeBu® Empower emulation system enables verification teams to exploit realistic software payloads when analyzing the power characteristics of their SoC hardware. In this blog, we will explore the challenges of full chip-level power signoff using ZeBu Empower in more detail.