Realize Up to 5x Faster Timing Signoff with FlexEDA

Timing closure for a chip is like setting the timing chain (or belt) in a vehicle with an internal combustion engine. If the timing chain is not synchronized correctly, the vehicle will perform poorly, and the engine could fail. Similarly, if timing for a chip is not closed properly, the chip will not meet specifications and may not be functional.

As semiconductor chips become increasingly complex, timing closure is even more critical to first-pass silicon success. At a high level, timing closure needs to be done at the block, sub-system and full-chip levels, and now across dies in multi-die designs.

A challenge as we go lower in technology nodes is the huge explosion in the number of Process, Voltage and Temperature (PVT) and RC conditions. Making sure chips are functional across the entire spectrum of PVT conditions is a daunting and time-consuming task. Another hurdle is increasing design size with billions of instances and hundreds of timing scenarios to cover. To overcome these challenges there is a need to run exhaustive analysis and perform fixes faster to achieve final signoff. Getting results faster is critical for timing engineers to accelerate design closure and meet tapeout schedules.

In this blog we will learn about the latest innovative cloud compute and Synopsys Cloud FlexEDA Pay-Per-Use licensing that together can help achieve results faster using PrimeTime® to accelerate timing signoff.

Semiconductor design companies, small or big, have a few challenges in common and everyone has their own way of overcoming them.

• Explosion of Process, Voltage and Temperature (PVT) and RC conditions: To make sure a chip is functional across hundreds of scenarios is complex. Chip validation is longer due to increasing number of blocks and instances affecting overall design size.
• Process and On-Chip variations: It is important to consider process variations and on-chip variations especially for lower and newer nodes that are not yet mature or have shown variations despite being mature. This adds another layer of complexity for timing closure and signoff. 
• Advanced process effects: Increased process complexity in designs from new effects such as aging, IR, thermal and stress. 
• First pass silicon success and time to market: Achieving silicon success is the goal for chip designers. Getting it right the first time is mission critical and timing closure is the foundation for a robust chip. Another key aspect is to be first to market and be able to benchmark the chip with customer validations. 
• Differentiation: Ability to provide a differentiated offering with best-in-class Power, Performance, Area (PPA) and cost.

Synopsys brings a unique value proposition to address each of these challenges. 

• The Synopsys PrimeTime suite delivers fast, memory-efficient scalar and multicore computing, distributed multi-scenario analysis and variation-aware modeling. The PrimeTime static timing analysis solution provides a single, golden, trusted signoff solution for timing, signal integrity, power and variation-aware analysis.
• Full license management automation via Synopsys Cloud FlexEDA provides access to the entire suite of EDA products and Hardware Assisted Verification solutions to meet design needs and help exceed PPA targets with quality tapeouts the first time.
• Access to the latest computing resources in the cloud helps to deliver better performance for EDA workloads.
• Seamless access to the complete Synopsys IP portfolio offering Industry leading Power, Performance and Area helps designers achieve first pass silicon success while ensuring their product specifications are met within schedule.

Synopsys Cloud customers are getting up-to 40% improvement in engineering productivity and accelerated time to results ranging from 2x-52x with patented FlexEDA pay-per-use by the minute access to highly scalable tools used at various stages of chip development.

The underlying hardware on which software runs impacts time to results. This is why Synopsys Cloud SaaS offers the latest and greatest compute to designers. Utilizing advanced compute resources in the cloud along with on-demand, unlimited pay-per-use FlexEDA licensing, chip design workloads can run up to 52x faster. The result is accelerated tapeout of a quality design that meets or exceeds product specifications.

With its 8.1 release, Synopsys Cloud SaaS now offers compute virtual machines (VM) powered with 5th Gen Intel® Xeon® Platinum 8573C (Emerald Rapids) and 4th Generation AMD EPYC™ Genoa based on x86 architecture. These machines offer faster performance for EDA workloads. We see 2.6x faster time to results for timing signoff with PrimeTime on these new VMs.