As meeting dynamic power requirements becomes increasingly difficult, chip designers often consider power to be their top verification challenge. Dynamic power verification requires finding peak power. Yet, critical peak power events are driven by actual software workloads. Simulation can identify peak power that falls above as well as below the power budget, but in billion-gate designs, it will only be able to catch the real critical events by pure luck, as the windows a simulation-based approach can consider are much too small. A signoff tool would provide accurate power measurements, but if it is used on the wrong time window, the designer would not be able to determine which window has the highest power.
Identifying low-power bugs requires running software workloads. Small tests won’t expose realistic workload-driven power bugs. What’s needed is:
- Real firmware and operating system at pre-silicon testing
- Emulation to verify power over millions or billions of cycles
- Pre-silicon power verification for debug, which isn’t possible with actual silicon
High-speed emulation allows design teams to perform power verification earlier in the design cycle, so they can minimize the risks of power bugs and missed SoC power goals. Indeed, a fast power emulator can be the answer to the hardware/software power verification dilemma, providing better accuracy across a broader window. The ideal emulator would be able to run multiple iterations a day on large designs with realistic workloads. By doing so, chip designers can gain actionable insights into the power profile of their designs.