The artificial intelligence (AI), automotive, internet of things (IoT), and mobile industries have seen significant progress in the last few decades, powered by advanced nodes (think 10nm and under) that are designed using digital technology tools dependent on accurate libraries that map to the latest process technologies.
Designers and foundries use high-quality libraries, the building blocks for system-on-chip (SoC) designs, to decrease time to market and ensure optimal implementation and manufacturability. These technology libraries become increasingly complex as the advanced nodes scale and there is a need for more accuracy for the process, voltage, and temperature (PVT) conditions. Usually, library characterization takes months and with each advanced node, the challenges grow to include a tripling of PVT corners, variation modeling, reliability, and aging effects.
If signoff libraries for advanced process nodes are not available in a timely manner, this can translate to a massive bottleneck for chip designers, potentially delaying project schedules and, consequently, the latest and greatest mobile device, IoT gadget, advancement in autonomous driving technology, etc.
In addition, the smaller the geometry of an SoC is, the lower the margin for error. Accurate modeling is key for advanced nodes. For instance, in variation modeling, the objective is to model how the device will behave when there is a slight change in PVT. A small variation in advanced nodes may be the difference between a working device and an inoperable one.
That’s why Synopsys announced PrimeLib today at our SNUG® World international user conference. PrimeLib is a high-performance, comprehensive characterization and validation solution that produces signoff-quality libraries targeted for SoC design at advanced process nodes. It’s a key enabler for correct-by-construction design as we scale into unprecedented levels of complexity and deal with new manufacturing challenges.