Creating the next generation of chip design engineers needs to start at the university level. Consider a project involving a complex 5nm design, which would require a team for implementation, verification, software design, and more. Such an endeavor could involve more than 100 people who have the latest skills. However, it’s not always easy to find the right mix of engineers.
Israel, for example, is in a region of the world where the dearth of electronic design talent is extremely high. To help create a pipeline of engineers, Zvi Webb, a retired applications engineering director from Synopsys, is serving as VLSI lab manager at Tel Aviv University and is developing an introductory very large-scale integration (VLSI) course based on the latest chip design tools. Students there, Webb noted, hadn’t been exposed to a digital design workflow and tool chain. Instead, they were building their designs manually.
Webb’s course will be offered in the spring of 2022 and will cover topics such as Verilog, logic synthesis, static timing analysis, and placement and routing, providing students with real-world expertise that can help open doors once they’re ready for the workforce. The training outline was derived from material prepared by Professor Adam Teman from Bar Ilan University. “The new course will bring student engineers more knowledge – they will gain an understanding of what VLSI means, what the steps are, how to perform checks,” Webb said.