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For artificial intelligence to become the next great global economic engine, it will require an entirely new means of production.
Tech giants are betting hundreds of billions of dollars on a future powered by AI. McKinsey projects investments of as much as $7 trillion in AI-related data centers by 2030 — one of the largest infrastructure buildouts in history, surpassing previous technology booms in both scale and pace.
Among the most ambitious are Meta’s 1-gigawatt Prometheus AI supercluster in New Albany, Ohio, and its 2,250-acre 5 GW Hyperion facility in Richland Parish, Louisiana. Stargate, a joint $500-billion venture by OpenAI, Softbank, and Oracle, is building 10 GW of AI data center capacity across multiple U.S. locations, including a 1,100-acre campus in Abilene, Texas. Google, Microsoft, Amazon, Apple, and others are similarly constructing new, massive data centers.
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Beyond just big
But size isn't everything. Even as data centers have grown larger and more powerful, AI demands a distinct computing architecture — a shift that makes the transition from mainframe to the cloud seem rather quaint.
The growth of AI represents a fundamental transformation in how the world builds and operates computing infrastructure. While traditional data centers are designed for general-purpose workloads, AI superclusters are purpose-built facilities that function as industrial-scale intelligence production systems. And their output is defined by new metrics — most notably tokens per watt and tokens per dollar — that quantify the efficiency and productivity of intelligence at scale.
As NVIDIA CEO Jensen Huang has put it: “AI is now infrastructure, and this infrastructure, just like the internet, just like electricity, needs factories.”
Building for AI production
To generate and process the massive volumes of data across the full spectrum of AI production — from data ingestion and model training to fine-tuning and large-scale inference — AI data centers need to overcome enormous engineering design challenges.
Addressing these complex issues requires a transformative approach that impacts every aspect of the system design and its individual components, right down to the silicon itself.
- Specialized AI chips. To handle massive parallel computations and real-time inference, the semiconductor industry is innovating with specialized AI chips, including graphic processing units (GPUs), application-specific integrated circuits (ASICs), and custom accelerators like neural processing units (NPUs). Although these deliver extreme performance per watt, they also push up power density, thermal load, and interconnect complexity, which in turn requires re-engineering boards, racks, and facility infrastructure to maximize their performance.
- Interconnect bottlenecks. AI training runs require terabytes of data across thousands of compute nodes, and even the highest-speed links between chips and server components can present bottlenecks. As a result, AI data center servers need optimized GPU‑to‑GPU links, CPU‑to‑memory buses, PCIe, and rack‑scale fabrics to achieve ultra‑low‑latency, high‑bandwidth communication between chips or nodes.
- Memory constraints. A related challenge is memory. Training complex AI models requires substantially larger memory pools and high-bandwidth memory (HBM) to avoid hitting the “memory wall” — a situation where insufficient memory forces frequent data transfers to slower storage tiers, dramatically reducing performance. To feed specialized AI chips with as much data as they can process, system designers need to place optimized memory close to the processors running the AI workloads.
- Advanced packaging. To deliver the performance at scale that AI requires, silicon designers are increasingly turning to multi-die designs, including 3D integrated circuits (3DICs) and chiplet-based architectures. While these chip designs offer gains that traditional monolithic SoCs cannot achieve cost-effectively, they also introduce significant complexity to the design process.
- Security. Complex, multi‑die SoCs, chiplets, and high‑bandwidth interconnects introduce an expanded attack surface, where a single weak link in the silicon or protocol stack can expose entire clusters to compromise. Protecting models and data now requires end‑to‑end cryptographic safeguards across memory, PCIe, and network fabrics, plus a silicon-level security stack, to ensure the integrity and confidentiality of workloads in motion and at rest.
Challenges at scale
The challenges of AI production do not stop at the servers. Training clusters span tens of thousands of GPUs, so facilities must be capable of supporting higher rack densities, gigawatt‑class campuses, and rapid capacity growth — all of which are essential for growing AI compute workloads.
- Networking. Poorly designed data center networks leave GPUs idle, and the bandwidth capabilities of traditional “leaf-and-spine” cabling models won’t cut it. AI servers demand four to five times more fiber connections with high-bandwidth, ultra-low-latency fabrics that use multiple specialized technologies.
- Power management. Some AI factories can consume as much energy as a small city. Racks drawing 30–100 kW or more — equivalent to approximately 75-100 homes — represent a 10× increase in power density compared to traditional data centers. And the power requirements of next-generation racks are set to rise. Achieving sustainable power usage requires multi-layered strategies, including at the silicon level. Designing chips for high power densities that stay within tight energy and cooling budgets makes power delivery not just a circuit issue, but a packaging and system‑level problem. Every milliohm in the power path turns into heat that must be removed without throttling performance. At the same time, minimizing data movement on-chip helps ensure each joule delivers more productive AI tokens, reducing stress on both the data center power system and its cooling infrastructure.
- Thermal management. As far as heat goes, the math is simple: more racks of AI servers = more heat. Traditional data center air cooling is insufficient, and once again, what happens at the silicon level has an exponential impact. Thermal loads are highly concentrated and continuous under AI training workloads, creating hot spots in both the silicon and the stack that require more aggressive heat‑spreading, advanced materials, and liquid cooling to avoid reliability loss and clock throttling.
Enabling a new economy
Building AI factories demands coordinated innovation, with end-to-end security, energy efficiency, and thermal management — from the foundational silicon to the fully-scaled supercluster campus. Tackling these highly interconnected challenges requires tools and IP that help engineers design and develop across chips, packages, boards, racks, and entire systems.
Synopsys delivers those capabilities in a few ways. First, our broad portfolio of foundation, interface, and security IP give designers trusted, silicon-proven solutions for high-performance AI chips and interconnects. And our industry-leading EDA, simulation, analysis, and lifecycle management tools give teams the ability to develop hardware, advanced packaging, and software in unison while optimizing their designs for power, performance, and area (PPA).
Finally, with the integration of Ansys multiphysics technologies, we now support chip‑to‑system simulation of power, thermals, signal integrity, and fluid dynamics. This gives engineering teams a powerful way to design AI factories that are not just powerful, but also energy efficient and reliable at scale.
Computing reimagined
As artificial intelligence rewires how the world uses technology, it also signals a fundamental reconceptualization of computing infrastructure as industrial production capacity. The scale of investment, technical complexity, and strategic importance of these projects position AI factories as the foundational infrastructure for the next era of technological advancement — and we look forward to helping make it a reality.
An edited version of this article originally appeared in Express Computer
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