Predicting Silicon Behavior Years before Test Wafers

Semiconductor engineers have known for decades that serial fabrication runs of test wafers is an inefficient way to bring up new processes and technologies. Modern deep submicron nodes have only reinforced this observation. It now costs several years and tens of billions of dollars just to build a fab. Every test wafer run takes months and costs millions. Finding problems after a run, figuring out the causes, devising fixes, and waiting for the next set of wafers to confirm the results is just not feasible anymore.

The only solution is an electronic design automation (EDA) toolset that can accurately predict chip behavior before any wafers are run, and even before the fab is ready. This enables the very first test wafers to closely match the desired characteristics. It also minimizes the number of tweaks and fab runs needed to refine the process for production designs. Synopsys S-Litho™, which provides early lithography pathfinding, process optimization, and analysis, is a prime example of such a solution. Recent results demonstrate dramatically the accuracy of its predictions years before test wafers are available.

In 2021, Synopsys engineers used S-Litho to simulate high-NA (numerical aperture) EUV (extreme ultraviolet) lithography for a 22nm pitch. The analysis predicted about a 0.5 nm line width roughness (LWR) for horizontal (H) compared with vertical (V). Since line edge roughness (LER) is generally a bit more than half of LWR, the LER prediction was therefore around 0.3 nm for H compared to V. S-Litho also predicted a 50% failure rate reduction for H versus V lines. These predictions were published in May 2021 in the Journal of Micro/Nanopatterning, Materials, and Metrology¹:

It took several years for equipment to be developed, fabs to be built, and test wafers to be run. Actual 21 nm silicon results were presented by IBM at the International Conference on Extreme Ultraviolet Lithography² in 2025 and at Optical and EUV Nanolithography XXXIX³ in 2026. These results showed that vertical lines had LER of 1.6 nm and horizontal lines LER of 1.3 nm, the 0.3 nm difference predicted four years earlier by S-Litho. The graphs below show the reported LER measurements for horizontal lines on the left and vertical lines on the right.

S-Litho provides physics-based, end-to-end lithography simulation independent of WFE development and long before test wafer results. The IBM silicon measurements testify to the accuracy of S-Litho LER predictions. IBM could not (yet) report real-world failure rates since it takes millions of parts in production to establish a failure history. The ability of S-Litho to predict failure rates before test wafers, let alone full production, is highly valuable.

S-Litho's power and accuracy have important benefits for the semiconductor industry. For advanced nodes with high-NA EUV lithography, early, trusted prediction reduces risk and guides process and design tradeoffs. It also informs the selection of hardware and software development tools. Accurate predictive simulation is a prerequisite for technology leadership.

These results also have positive implications for Synopsys Proteus™ full-chip mask synthesis smart manufacturing solutions. High-NA Proteus OPC (Optical Proximity Correction) was built and validated using S-Litho. Thus, chip developers can also count on Proteus results before silicon is available. The number of test wafer runs is dramatically reduced. If process tweaks are made, S-Litho can check to see if the desired effects will be achieved without waiting for a new fab run. As fab times continue to elongate, any reduction in test wafer runs saves enormous time and cost.

The ability to predict future lithography behavior has become a strategic enabler for semiconductor development. S-Litho is the first wafer-validated optical simulation solution for high-NA EUV applications. Process developers no longer have to wait for next-generation equipment or fabs. S-Litho is a key step toward the industry goal of having true digital twins for processes.