IC Validator WorkBench

High Speed Layout Visualization



IC Validator WorkBench (ICVWB) is a powerful, high-performance, hierarchical layout visualization and analysis tool. It allows quick viewing and editing GDSII, OASIS®, and LEF/DEF layouts from small IP blocks to full-chip databases. In addition, ICVWB enables you to easily visualize and access the layout data being examined by the IC Validator (ICV) physical verification tool suite and review physical verification results. Building from the earlier IC WorkBench Edit/View Plus (ICWBEV) product, ICVWB refines the application for physical verification designers.


  • Quickly opens large GDSII, OASIS, and LEF/DEF files with low memory overhead.  Additionally, cache files can drastically decrease the time for subsequent sessions
  • Opens Optimized OASIS files instantly
  • Provides easy debugging of the hierarchy and placement of cells and shapes
  • Quickly determines and displays shape connectivity interactively with cut layer capabilities
  • Provides improved support of the IC Validator (VUE) application to review and correct DRC and LVS errors
  • Provides various modes for merging layouts of mixed formats and DBUs
  • Compares layouts, cells, and generates difference reports/layouts
  • Defines TCAD simulation domains in hierarchical layouts for Sentaurus


High Speed, High Capacity View and Editing

Figure 1: Hierarchical selection and editing in ICVWB

ICVWB loads gigabytes of data in minutes and has unlimited file size capacity on 64-bit platforms. Fast zooming and panning ease exploration and analysis of the largest layout patterns. In addition, ICVWB can overlay two or more layouts in a single view without merging the underlying layout files.

Hierarchical selection and editing allow ICVWB to select and edit shapes deep in the hierarchy without requiring the sub-cell to be opened as shown in Figure 1. Edit operations have undo and redo support.