IBM’s Experience with IC Validator DRC Explorer to Achieve Fastest DRC Results
Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip DRC and LVS
NVIDIA’s Experience with IC Validator for Physical Signoff of Full Reticle GPU Designs
Socionext Shares Their Experience with IC Validator for Excellent Performance Scalability
Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area while accelerating their ever-important time-to-market.
Metal fill insertion affects timing because of added capacitance. Balancing density requirements and timing on critical nets is crucial for timely design closure. IC Compiler II In-Design with signoff quality metal fill minimizes the timing impact of metal fill and reduces overall design turnaround time.
In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage of the integration of the IC Compiler II with signoff quality DRC checking, designers can automatically fix DRC violations and improve turnaround time by automatically detecting changed ECO areas for incremental DRC checking.
Learn how to execute fill in the tool.
Learn how to connect VUE with IC WorkBench EV Plus, IC Compiler, IC Compiler II and, Cadence Virtuoso tools.
Learn how to use the Error Heat Map to debug DRC errors.
Learn how to use the Connect Debugger utility from the VUE tool.
Learn how to load a replay file in the VUE tool.
See how to debug results in IC Compiler II using the VUE tool.
Learn how to run Signoff DRC in IC Compiler II tool.
Learn how to create a pattern library.
Learn how to perform Pattern matching in the tool.
Learn how to create a pattern library using the Pattern Library Manager.
Learn how to run the tool on multiple CPUs from the same or different machines.
Learn how to add a host to a job that is already running.
Learn how to create and use waivers using the VUE tool.
Learn how to create and use waivers using the PYDB utility.
Learn how to generate an ASCII format error file from the PYDB database.
Learn how to generate layout errors files from the PYDB database.
See an overview of the run_options() function.
See an overview of the error_options() function.
See an overview of the hierarchy_options() function.
See an overview of the text_net() function.
See an overview of the text_options() function.