Video Resources

To learn about Synopsys' Physical Verification solutions go here

Technical Video Series by Topic

DRC    LVS    Fill    VUE     In-Design    Pattern Matching    Distributed Processing     Waiver Flow     PYDB    Tool Functions    Documentation             

Customer Experiences

IBM + -

IBM’s Experience with IC Validator DRC Explorer to Achieve Fastest DRC Results

Juniper + -

Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip DRC and LVS

NVIDIA + -

NVIDIA’s Experience with IC Validator for Physical Signoff of Full Reticle GPU Designs

Socionext + -

Socionext Shares Their Experience with IC Validator for Excellent Performance Scalability

Synopsys Videos and Tech Talks

Fusion Technology: Broadly Addressing the Challenges of 5-nm-and-Below Processes

Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area while accelerating their ever-important time-to-market.

How to Minimize the Impact of Metal Fill on Timing?

Metal fill insertion affects timing because of added capacitance. Balancing density requirements and timing on critical nets is crucial for timely design closure. IC Compiler II In-Design with signoff quality metal fill minimizes the timing impact of metal fill and reduces overall design turnaround time.

How to Reduce the Amount of Time to Fix DRCs Near Tapeout?

In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage of the integration of the IC Compiler II with signoff quality DRC checking, designers can automatically fix DRC violations and improve turnaround time by automatically detecting changed ECO areas for incremental DRC checking.

DRC Videos

Learn how to setup the tool in your environment and how to change tool versions. 

Learn how to run DRC on your shell.

Learn how to run DRC interactively from the VUE interface. 

Learn how to select/unselect rules functions within the rule deck file. 

Learn how to run incremental DRC flow by Layer/window options. 

Learn about the output files such as  Result, Error, Summary, Tree, distributed log file. 

Learn about Layer debugger from the VUE tool. 

 

Learn about how the LVL utility compares two layout files and flags the differences.

Learn about how Quick LVL points out the location of differences.

Learn how DCV Analyzer tool analyzes the performance and hierarchy of a run. 

Learn how to compare DRC results using the DCV Results Compare Tool tool.

Learn  how to use cal2pxl utility. 

Learn how to execute a run-only job.

Learn  how to check runset syntax and generate a partially compiled runset.

Learn how to exit a job with partial results.

Learn how Explorer detects design rules such as width, spacing, and interacting checks from the foundry runset. 

LVS Videos

Learn how to run LVS Schematic  from your shell.

Learn how to run Layout -Vs-Schematic interactively using VUE. 

Learn how to run only extraction or only compare in the LVS flow. 

Learn how to create an equivalence file for LVS run. 

Learn how to use Edtext file.

Learn how LVS Black Box allows you to validate top-level designs.

Learn about NetTran netlist translation utility. 

Learn how to compare two netlists of any format like SPICE, IC Validator or VERILOG using NVN utility. 

Learn how to compare LVS results using DCV results compare tool.

Learn how to use the net trace utility to debug LVS results. 

Learn how to use the Short Finder function to debug text and compare shorts.

Learn about  output files available after an LVS run.

Learn how to fix GNFerror during LVS run.

Fill Videos

Learn how to execute fill in the tool.

VUE Videos

Learn how to connect VUE with IC WorkBench EV Plus, IC Compiler, IC Compiler II and, Cadence Virtuoso tools. 

Learn how to use the Error Heat Map to debug DRC errors. 

Learn how to use the Connect Debugger utility from the VUE tool.

Learn how to load a replay file in the VUE tool.

In-Design Videos

See how to debug results in IC Compiler II using the VUE tool.

Learn how to run Signoff DRC in IC Compiler II tool.

Pattern Matching Videos

Learn how to create a pattern library.

Learn how to perform Pattern matching in the tool. 

Learn how to create a pattern library using the Pattern Library Manager.

Distributed Processing Videos

Learn how to run the tool on multiple CPUs from the same or different machines.

Learn how to add a host to a job that is already running. 

Waiver Flow Videos

Learn how to create and use waivers using the VUE tool.

Learn how to create and use waivers using the PYDB utility.

PYDB Videos

Learn how to generate an ASCII format error file from the PYDB database. 

Learn how to generate layout errors files from the PYDB database.

Tool Functions Videos

See an overview of the run_options() function. 

See an overview of the error_options() function. 

See an overview of the hierarchy_options() function. 

See an overview of the text_net() function. 

See an overview of the text_options() function. 

Documentation Videos

Learn where to find documentation.