Memory Compilers

Synopsys Embedded Memory IP, a cornerstone of Synopsys Foundation IP portfolio, features a comprehensive range of Memory Complilers, Duet Packages and HPC Design Kits. These solutions support a broad array of foundries and process technologies, spanning from 250-nm to 2-nm. Proven in silicon, Synopsys Embedded Memories have enabled billions of chips to ship in volume, helping designers reduce risk and accelerate time-to-market.

Optimized for low power, high performance, and high density, Synopsys Memory Compilers offer advanced power management features—including light sleep, deep sleep, shut down, and dual power rails—to help designers meet strict low-power requirements of modern SoCs. The compilers support multiple operating PVTs, including temperature inversion corners, and provide flexible modes for data retention or shut down, ensuring efficient operation across varied conditions. For greater reliability and yield, Synopsys Memory Compilers integrate with the Synopsys STAR Memory System™, delivering test solutions that detect and repair faults while reducing chip area.

The Synopsys Memory Compilers portfolio includes configurable and specialty compilers for diverse architectures. Configurable compilers include Embedded SRAMs (single/dual port) and Multi-Port Memory Compilers, available in high-speed (HS), high-density (HD), ultra-high density (UHD), and extreme high-density (EHD) architectures. These minimize area and power while meeting aggressive timing requirements. EHD, UHD, and HD compilers focus on reducing area and power, while HS compilers deliver peak performance. EHD compilers offer the smallest area footprint.

In addition, Synopsys specialty compilers—MRAM, RRAM, TCAM—are highly optimized to address the high-performance and low-power needs of emerging SoC applications.