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Synopsys Power Optimization Kits (POKs) enable designers to minimize power consumption while maintaining optimal performance. Available for Synopsys Logic Libraries at 65 nm and below, these kits include a set of specially designed cells that allow designers to shut down portions of a design to save power. Additionally, Synopsys POKs support dynamic operation of functional blocks at multiple voltages, enabling optimal trade-offs between dynamic power consumption and performance across various operating modes.
POK Components
Highlights
- Power Down Inactive Blocks on Chip
- Save system power by powering down unused functions
- Power gates manage shutdown and power-up
Features
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- Patented circuits and structures for power optimization
- Power-gating for domain shutdown
- Maximum power savings
- Multiple drive strengths enable fast wake-up times
- With and without enable for daisy chain or high fan-out structures
- Well modeling of bulk pins for clean LVS flow
- Level shifters for multiple voltage islands
- Up, down, up/down shifters
- Wide shifting range from low voltage, standard voltage to overdrive
- Isolation cells to prevent unknown states from unpowered domains
- Data retention flip-flops
- Standard save-restore latch flops
- Live latch flops avoid area penalty of save-restore latch flops
- Always-on cells powered by retention supply rail
- Pitch matched to high-density, high-speed and ultra high-density cells
- Available in standard and high VTs
- Biasing cells for leakage control
- Support for industry-standard EDA power flows
- UPF and CPF
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