RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.

Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications. Originally developed at the University of California, Berkeley, the RISC-V ISA is considered the fifth generation of processors built on the concept of the reduced instruction set computer (RISC). Due to its openness and its technical merits, it has become very popular in recent years. The standard is now managed by RISC-V International, which has more than 3,000 members and which reported that more than 10 billion chips containing RISC-V cores had shipped by the end of 2022. Many implementations of RISC-V are available, both as open-source cores and as commercial IP products. 

How does RISC-V work?

As an open-standard architecture, RISC-V is defined by member companies of RISC-V International, the global nonprofit organization behind the ISA. The intent is that through collaboration, the member companies can contribute new avenues of processor innovation while promoting new degrees of design freedom.

The royalty-free RISC-V ISA features a small core set of instructions upon which all the design’s software runs. Its optional extensions allow designers to tailor the architecture for a variety of different end markets. Essentially, the RISC-V architecture allows designers to customize and build their processor in a way that’s tailored to their target end applications, so they can optimize the power, performance, and area (PPA) for those applications. The RISC-V ISA also provides the flexibility to pick and choose from available features, rather than having to use the full feature set.

While the initial market adoption of RISC-V has been with embedded applications and microcontrollers, the open-source architecture also holds promise for high-performance computing and data centers. 

The history of RISC-V

RISC-V began as a project at UC Berkeley to create an open-source computer system based on RISC principles. It was initially designed for academic use. The standard has evolved and is now managed by RISC-V International. 

The RISC-V International organization has moved its headquarters to Switzerland to maintain neutrality for designers worldwide without any government regulations. 

The ecosystem is emerging and growing to support the standard. As the adoption rate accelerates,  industry collaboration continues, further evolving the architecture.  

What are the benefits of RISC-V?

RISC-V has gained popularity because the architecture provides simplified instructions to the processor to accomplish various tasks. It also enables designers to create thousands of potential custom processors, facilitating faster time to market. The commonality of the processor IP also saves on software development time.   Other benefits of RISC-V include:

  • Its open-standard nature, which allows collaboration and innovation across the industry 
  • Common ISA, which helps make software development easier since all processors could potentially use the same architecture. Designers can use the same base ISA, from simple embedded devices to the largest supercomputers, tailoring their device to the needs of the market. Compared to previous ISAs, RISC-V ISAs have unique features and can be customized based on their requirements. 
  • Availability of smaller, energy-efficient, and modular options  
  • Security features, which are available through open-source reference designs, software composition analysis tools, and security extensions. In addition, its open-source nature means that the entire RISC-V architecture can be scrutinized closely in the public domain, eliminating back doors and hidden channels.  

What are key RISC-V applications?

The application options are endless for the RISC-V ISA:  

  • Wearables, Industrial, IoT, and Home Appliances. RISC-V processors are ideal for meeting the power requirements of space-constrained and battery-operated designs.  
  • Smartphones. RISC-V cores can be customized to handle the performance needed to power smartphones, or can be used as part of a larger SoC to handle specific tasks for phone operation. 
  • Automotive, High-Performance Computing (HPC), and Data Centers. RISC-V cores can handle complex computational tasks with customized ISAs, while RISC-V extensions enable development of simple, secure, and flexible cores for greater energy efficiency.  
  • Aerospace and Government. RISC-V offers high reliability and security for these use applications. 

Who's using RISC-V?

The industry is seeing a large amount of interest in this processor IP. RISC-V IP is expected to grow at a compounded annual growth rate of 35% projected through 2027. There are three main market segments interested in the RISC-V architecture:

  • IP providers who can offer their own designs
  • SoC teams using commercial IP
  • Designers building custom, RISC-V processor-based SoCs

RISC-V Design and Verification Challenges

RISC-V presents special challenges because its specification is designed to provide a configurable and customizable solution for general-purpose processors. There are many options and variations defined in the ISA specification, and users are permitted to extend the ISA even further by adding custom instructions. Therefore, any RISC-V verification solution must be flexible enough to accommodate customizations.

Similarly, as the RISC-V architecture is being adopted for high-end applications like HPC and mobile, the PPA requirements are also demanding, which requires industry-leading design automation tools and methodologies.

What solutions does Synopsys offer?

Synopsys, a strategic member of RISC-V International, has been supporting processor IP development and optimization for the best PPA for leading-edge designs for more than three decades. If end customers decide to develop a RISC-V ISA, Synopsys is uniquely positioned to help those companies design and fully verify RISC-V SoCs. Electronic design automation (EDA) tools from Synopsys provide a powerful out-of-the-box RISC-V development and verification combination. Synopsys IP can be easily extended to host any RISC-V core.  

  • Synopsys ARC-V™ processor IP includes high-performance, mid-range, and ultra-low power RISC-V processor options, as well as functional safety versions, to deliver optimal power-performance efficiency for a broad range of application workloads. Synopsys ARC-V™ Processor IP is supported by the growing RISC-V ecosystem, giving developers a menu of choices to build a flexible environment with all the required development tools. Also supported is the trusted Synopsys MetaWare Development Toolkit, which includes all of the components needed to develop, debug and optimize embedded software for ARC-V Processor-based designs.
  • RISC-V design and implementation: Synopsys Fusion QuickStart Kits (QIKs) include implementation scripts, reference guides, and a baseline floorplan so designers don’t need to start from scratch. Utilizing QIKs and leveraging the Synopsys Fusion Compiler™ RTL-to-GDSII design product and Synopsys Design Space Optimization (™) AI application for chip design can accelerate the development of RISC-V-based SoC designs. Synopsys is partnering with SiFive to offer Fusion QuickStart kits for SiFive's Intelligence™ X280, Performance™ P550, and future processor cores 
  • RISC-V verification: Reference methodologies for the verification and debugging of RISC-V system designs are available now, along with Synopsys EDA flows, emulation and virtual prototyping solutions, and methodologies to further support RISC-V SoC verification. Collaborative efforts include:  RISC-V verification methodology cookbook for Bluespec cores, "Understanding UVM Coverage for RISC-V Processor Designs" white paper, RISC-V and processor verification using ImperasDV verification solutions, and the industry-leading Synopsys VCS® simulation and Verdi® debug tools for improved efficiency (see news release).
  • Custom designs with Synopsys ASIP Designer: ASIP Designer helps teams build a custom RISC-V processor through architecture exploration. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++ compiler-based software development kit that automatically adapts to every architectural change, and automatic generation of power and area-optimized, synthesizable RTL. 
  • RISC-V PPA measurement with Synopsys RTL Architect:  RTL Architect is a multi-dimensional implementation prediction engine that enables RTL designers to predict the PPA and congestion impact of their RTL changes. 
  • Synopsys Interface IP: Thousands of customers trust Synopsys IP in their SoCs, minimizing risk and accelerating time to market. Synopsys provides the industry’s broadest portfolio of complete, silicon-proven IP solutions, with leading PPA and security for the most widely used interfaces such as PCI Express®, CXL, USB, Ethernet, DDR, HBM, Die-to-Die, CCIX, MIPI, HDMI, and Bluetooth
  • Virtual Prototypes: Early SW development with Synopsys Virtual Prototyping, includes Virtualizer™ for the creation of virtual prototypes for software development with the industry's largest portfolio of transaction-level models (TLMs). Specific RISC-V TLM models include those for SiFive, Andes, OpenHW, lowRISC, as well as Synopsys ARC-V cores. Ready-to-use Virtualizer Development Kits (VDKs) and Starting Point VDKs for many platforms, turn-key and ramp-up services to ensure project success, are also available.
  • Enhanced security: Synopsys Black Duck® software composition analysis solution helps design teams manage the security, quality, and license compliance risks that can come from using open-source and third-party code in applications and containers.

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