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ARC Processor IP QuickStart Implementation Kits
Accelerate your ARC Processor IP Designs
Optimizing a processor design for a specific application’s power, performance and area (PPA) goals requires a lot of manual effort, including writing tool scripts and performing multiple iterations to hit the right targets. Our processor IP and design implementations teams have been collaborating to help customers to maximize the PPA of ARC Processor designs.
Taking that knowledge and expertise, Synopsys offers Fusion QuickStart Implementation Kits (QIKs) for customers to download via SolvNet.
Watch the webinar to learn how to achieve higher PPA in ARC Processor implementations with AI-enabled Fusion QuickStart Kits.
Included in Fusion QIKs
Fusion QIKs for ARC processors include:
- Tool scripts
- Baseline floorplan
- Design constraints
- Documentation
Fusion QIKs leverage Synopsys’ Fusion Compiler RTL-to-GDSII design product and Synopsys Design Space Optimization (DSO.ai™). The Fusion Compiler solution helps push performance levels higher, while DSO.ai technology autonomously explores multiple design spaces to optimize PPA metrics while minimizing tradeoffs for the target application. With DSO.ai, teams can leverage AI automation to search for the best combination of requirements and find the best ARC processor design faster.
Access Fusion QIKs for ARC Processors
Synopsys offers Fusion QIKs for the ARC HS5x, HS6x, VPX and NPX processors. Visit the SolvNet Reference Methodology page to request a download today by selecting the QIK for Synopsys ARC Processor from the "Select a Product" dropdown menu.