The DesignWare® ARC® HS family, based on the efficient ARCv2 instruction set architecture (ISA), includes the HS3x, HS4x, and DSP-enhanced HS4xD processors. All HS processors support closely coupled memories (CCMs), which enable single-cycles access to instructions and data.
HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.
The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website.