ARC HS66 and HS68 Processors

The DesignWare® ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where high-performance and high clock speed are required. The processors can be clocked at up to 1.8 GHz in 16FFC processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 6.16 CoreMark/MHz with a small area footprint and low power consumption.

The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes(4.5x1015) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster.

The ARC HS66 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 16 MB and a Memory Management Unit (MMU).


DesignWare HS5x-6x Block Diagram

ARC HS66 and HS68 Block Diagram


ARC HS66 and HS68 Processors Datasheet

 

Highlights
Licensable Options
Products
Downloads and Documentation
  • Dual-issue, 64-bit processors for high-performance embedded applications
  • 52-bit physical and 64-bit virtual addressing
  • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
  • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
  • Based on advanced ARCv3 ISA
  • High degree of configurability
  • Enhanced MMU (HS68) with hardware page table walk and up to 16 MB page sizes
  • Support for custom instructions
  • Support for up to 16 MB of close coupled memory and direct mapping of peripherals
  • Floating Point Unit (FPU) supporting half, single- and double-precision IEEE 754-compliant operation
  • ARC Trace Interface provides real-time trace debugging features
  • Easy performance upgrade from HS3x and HS4x processors
Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processorsSTARs Subscribe
Memory management unit (MMU) option for ARC HS5x and HS6x processorsSTARs Subscribe
L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processorsSTARs Subscribe
ARC HS66MP multi-core version of dual-issue HS66 with I and D cache for high-performance embedded applicationsSTARs Subscribe
ARC HS66 64-bit, dual-issue processor core, interconnect, ARCv3 ISA, for embedded applicationsSTARs Subscribe
ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applicationsSTARs Subscribe
ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applicationsSTARs Subscribe

Description: ARC HS66 64-bit, dual-issue processor core, interconnect, ARCv3 ISA, for embedded applications
Name: dwc_arc_hs66_core
Version: 4.00a
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores
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Description: ARC HS66MP multi-core version of dual-issue HS66 with I and D cache for high-performance embedded applications
Name: dwc_arc_hs66mp_core
Version: 4.00a
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores
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Description: ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
Name: dwc_arc_hs68_core
Version: 4.00a
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores
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Description: ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applications
Name: dwc_arc_hs68mp_core
Version: 4.00a
STARs: Open and/or Closed STARs
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Description: L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
Name: dwc_arcv3_hs_shared_memory_option
Version: 4.00a
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores
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Description: Memory management unit (MMU) option for ARC HS5x and HS6x processors
Name: dwc_arcv3_hs_mmu_option
Version: 4.00a
STARs: Open and/or Closed STARs
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Product Type: DesignWare Cores
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Description: Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
Name: dwc_arcv3_hs_fpu_option
Version: 4.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information