Explore ASIP Events

Developing Your Own RISC-V Processor with Fast Architecture-Driven PPA Optimization

English

Seminar

This webinar will cover two products from Synopsys’ portfolio of industry leading tools: Synopsys ASIP Designer and Synopsys RTL Synopsys Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved.

Domain-Specific Processor Design using ASIP Designer

English

University Day 2022

At this informal event, leading university teams present results from their ongoing ASIP projects in a variety of application domains such as AI accelerators and smart vision systems. Synopsys shares insight on market trends, and provide a technical update on ASIP Designer along with reference examples.

ASIPs for 5G Wireless SoCs

English

Seminar

This seminar introduces you to the ASIP Designer tool-suite. It features two case studies.
The first case study by Lund University presents an application-specific vector processor for CNN based massive MIMO user terminal positioning. The ASIP contains a scalar RISC processor extended with a vector datapath and integrated accelerators.
The second case study by Synopsys shows an accelerator for 5G NR channel equalization. A RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for MMSE channel equalization using Cholesky Decomposition.

Designing ASIPs for Smart Vision Systems: A SLAM Case Study

English

Webinar

In this webinar you will:
Understand the trend of software-defined acceleration in advanced camera systems based on depth sensing technology;
See how the ASIP Designer tool suite enables you to design the correct ASIP architecture for such needs in a short period of time;
Observe what is followed in the actual design of the SLAM architecture design trajectory, including tool-assisted architecture and hardware optimization

Extending RISC Processors into Flexible Accelerators using ASIP Designer

English

Seminar

This seminar introduces you to the ASIP Designer tool-suite. It features two case studies from popular application domains.
The first case study, by the University of Virginia, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms, combining TVM and ASIP Designer. Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.
The second case study, by Synopsys, shows an accelerator for image signal processing. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.

Domain-Specific Processor Design using ASIP Designer

English

Seminar

Learn more about the power of ASIPs, and how ASIP Designer™ makes them a reality. This seminar covers the architectural options to choose from when designing an ASIP.
Using examples from the extensive processor model library that comes with ASIP Designer, we explain the different concepts of parallelization and specialization, and the tradeoffs that come with it.
The seminar includes demonstrations of ASIP Designer as well as an investigation of multiple example designs from the DSP, security, and AI domains.

Domain-Specific Processor Design using ASIP Designer

English

University Day 2021

At this informal event, leading university teams presented results from their ongoing ASIP projects in a variety of application domains such as 5G baseband and AI accelerators. Synopsys shared insight on market trends, and provided a technical update on ASIP Designer along with reference examples.

Efficient Dual Core LockStep Processor Design with ASIP Designer: An ST STxP5 Case Study

English

SNUG

To face increasing demand in SoCs for Functional Safety and Security, ST is developing custom processors implementing mechanisms that satisfy ISO26262 safety requirements and protect program execution against physical attacks.
In order to reduce the risk due to random faults and thus achieve high safety integrity, or to protect against physical attacks, logic duplication also called Dual Core LockStep (DCLS) is a commonly deployed method.
This presentation will explain how and why ST involved the Synopsys ASIP team in the development of a solution to increase the functional safety and security goals of the DCLS, and it will describe the process to generate the DCLS and its design results.

Domain-Specific Processor Design Using ASIP Designer

English

Seminar

The Fastest Path to Making an Open ISA Your Own
In this seminar learn why domain-specific processors gain a lot of attention these days, and why Synopsys’ ASIP Designer is the industry’s leading tool to design, implement, program and verify such specialized processors.