This seminar introduces you to the ASIP Designer tool-suite. It features two case studies from popular application domains.
The first case study, by the University of Virginia, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms, combining TVM and ASIP Designer. Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.
The second case study, by Synopsys, shows an accelerator for image signal processing. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.