ASIPs have established themselves as an implementation option next to standard processor IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability.  This talk will provide an introduction into Synopsys' ASIP Designer tool-suite, targeted markets, and how Synopsys collaborates with university partners in this domain.

Modern deep neural networks (DNNs) are composed of hundreds of heterogeneous layers with diverse configurations, often causing performance degradation on neural processing units (NPUs) due to frequent data layout mismatches. While each layer’s dataflow typically requires a specific data access order, the on-chip memory layout may not align with it, leading to bubble cycles for layout reordering. This overhead poses a key challenge to achieving efficient end-to-end DNN inference.

To address this problem, HopScotch introduces a holistic approach to data layout-aware mapping of DNNs on NPUs. HopScotch adopts a lightweight routing interconnect between on-chip memory and a systolic array using three-input multiplexers, paired with a programmable vector processor that performs arbitrary data layout reordering at runtime. It further introduces a tailored data layout to support diverse convolution configurations. At compile time, HopScotch employs a beam search–based Top-k layout mapping solver, efficiently exploring the vast layout mapping space and estimating costs with an analytical vector-processor model.

By co-optimizing its custom ISA, microarchitecture, and compiler mapping, HopScotch exemplifies the ASIP design methodology. This holistic approach substantially reduces layout reordering overhead, dramatically improving end-to-end DNN performance.

The separation of compute and memory creates a significant performance bottleneck. While wide vector units on 32-bit processors accelerate parallel computations, they remain limited by memory bandwidth. Near-memory computing (NMC) addresses this challenge by minimizing costly data movement. Using the Synopsys ASIP Designer, we extended a RISC-V CPU with a multiply-accumulate (MAC) systolic array tightly coupled to on-chip memory, enabling efficient NMC operations and accelerating a range of machine learning algorithms including brain-inspired hyperdimensional computing. The NMC operations are implemented in RTL and we integrated them into ASIP Designer to preserve C-level programmability and cycle-accurate simulation. The resulting chip was taped out in GlobalFoundries’ 22nm technology. The second part of this work extends the concept to a multi-core NMC architecture, demonstrating a system with five fully custom RISC-V processors and exploring the design challenges this raises within ASIP Designer. This 5-core chip, currently being fabricated in TSMC’s 7nm process, represents the first university-led tape-out in Germany using TSMC 7nm technology. Finally, we share our experience in delivering a hands-on ASIP Designer laboratory course at the Technical University of Munich (TUM), which supports up to 40 students and bridges advanced research in RISC-V with education.

Automotive functional safety remains a hot topic as AI drives automated driving toward large-scale deployment. Beyond component-level measures, we address the residual risk that persists and must be mitigated at system level. We propose a decentralized safety solution that implements external mechanisms under strict real-time constraints using hardware-accelerated AI and bare-metal software, bypassing the host RTOS to minimize latency. Our prototype detects anomalies in automotive CAN traffic with an AI model trained on validation test cases plus synthetic data derived from real scenarios. The model is authored in PyTorch, exported to ONNX, and translated to behavioral C. Using Synopsys ASIP Designer, we generate custom hardware resources, the HW/SW interface, and firmware; the processor fabric can target a RISC-V architecture. Design Compiler produces a gate-level netlist in a generic technology, and IC Compiler performs place-and-route to generate the controller layout ready for subsystem or system integration. The approach supports both primary and latent-fault safety mechanisms. This work underpins a student laboratory platform for the “Microprocessor Applications for Real-Time Systems” course in the “Electric Vehicle Propulsion and Control” master’s program at NUST POLITEHNICA Bucharest (academic year 2025–2026).

For supporting compute-intensive workloads in embedded systems, the use of parallel processing concepts is often required. In this presentation we review architecture features such as Single Instruction Multiple Data (SIMD) and static multi-issuing on a very-long instruction word (VLIW) architecture.  We will address the modelling of these features in nML and their support in the ASIP Designer Tool Suite. We will illustrate these architectural concepts at the hand of a few real-life designs from the wireless, AI and image processing domains.

ASIP Designer is used to analyze DSP kernel implementations on a 512-bit SIMD, six-instruction-slot VLIW VDSP processor prototype. The objective of this study is to investigate the efficient implementation of baseband kernels on a vector processor. The low-level VLIW instruction sequence, along with the detailed scheduling of micro-instructions across slots and cycles in the ASIP Designer instruction scheduling window offers clear visibility into kernel performance. Based on key kernel implementations, we identified inefficiencies in the compiled code and proposed optimizations at multiple levels of baseband processing—low-level, implementation strategy level, and algorithmic level—to achieve improved resource utilization. For our 5G RedCap IoT use case, we present optimization techniques that can be employed to enable a cost-effective VDSP-based modem solution.

ChronoMem is a memory-lifetime–aware, profiling-guided compiler and system for ASIPs built with Synopsys ASIP Designer. Using a ready-to-profile processor instance, we extend the testbench to log fine-grained LOAD/STORE traces, enabling characterization of data lifetimes. We then realize a mixed-memory hierarchy by integrating Gaincell memory into the cache path for short-lived data, while retaining SRAM for long-lived data. After an initial profiling run, ChronoMem feeds trace-derived lifetime information into the compiler, where we modify the intermediate representation to attach memory-placement attributes. The backend (Chess) uses these annotations to allocate objects to the appropriate memory type automatically. We describe the profiling hooks, IR extensions, and backend changes, and report on the resulting design trade-offs (area, leakage, and performance) observed on representative kernels. In this work, I also reflect on my experience learning and using the ASIP Designer toolchain—instrumenting the testbench, integrating custom models, and adapting the workflow to support profiling-guided compilation within the Synopsys environment.

The continuous evolution towards smarter, software driven, and often AI-powered electronic systems is driving ASIP Designer customers to design ever more advanced ASIP architectures, with larger amounts of instruction-level and data parallelism, deeper instruction pipelines and more architectural specialization.  In turn, this is driving Synopsys to continuously innovate and extend the scope of the ASIP Designer tool-suite.

In this presentation we review recent ASIP Designer tool innovations that empower architecture teams, RTL implementation teams and embedded software teams.  Among others, we zoom in on advanced software pipelining capabilities in the C compiler, faster instruction-set simulation, debugging and real-time tracing, and formal verification support for ASIP designs.