The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product.  By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated. 

Synopsys’ ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain. 

This seminar introduces you to the ASIP Designer tool-suite. 

It features two case studies from popular application domains. 

The first case study by Lund University presents an application-specific vector processor for CNN based massive MIMO user terminal positioning. The ASIP contains a scalar RISC processor extended with a vector datapath and integrated accelerators. 

The second case study by Synopsys shows an accelerator for 5G NR channel equalization. A RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for MMSE channel equalization using Cholesky Decomposition.


Listed below are the industry leaders scheduled to speak.

Patrick Verbist

Product Marketing Manager,

Synopsys Belgium

Patrick Verbist is the Product Marketing Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and, prior to the acquisition by Synopsys in 2014, Director of Sales at Target Compiler Technologies. Before Target, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven, Belgium.

Falco Munsche

Technical Marketing Manager

Synopsys Germany

Falco Munsche is the Technical Marketing Manager for Synopsys' ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.

Mohammad Attari

Digital ASIC Research Group, EIT

Lund University

Mohammad Attari is currently a PhD student in the Digital ASIC research group in the Electrical and Information Technology (EIT) department at Lund University. His research focuses on developing Massive MIMO and next generation baseband communications processors. His interests include (but are not limited to) computer architecture, domain specific architectures, accelerator-level parallelism, application specific instruction set processors (ASIP), neural networks, and cross-level hardware-software (-algorithm) codesign and implementation.

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