Contact Sales
Contact Sales
Our Company
Why Synopsys?

Our Technology, Your Innovation™. Trusted industry leader.

Learn more
Industry
Technology
Automotive Executive Guide: Rethinking Automotive Development

A guide to virtualization in software-defined vehicles for automotive leaders.

Download
By Function
Synopsys.ai
EDA
System
IP
SolvNetPlus SolvNetPlus gives instant access to docs, downloads, training, and self-help support resources online.
Training & Education Synopsys provides training delivered by subject matter experts, offering both public and private courses.
Learn
SNUG
Talk to an Expert

Rapid Program Tracing Spots Hard-To-Find Bugs
Synopsys SmaRT is a hardware module that can be integrated into any system-on-chip (SoC) within the Synopsys ARC configurable architecture. Delivered via the Synopsys ARChitect™ configuration tool as an IP library component, it enables rapid software debug with minimal increase in die size and no power consumption penalty.

Synopsys SmaRT gives developers the ability to trace program execution precisely in the real system. They can therefore diagnose bugs that are difficult to reproduce in system simulators, or only become apparent when the system is run at full speed.

The system works by recognizing any change of program flow control: the relevant source and destination instruction addresses are then recorded within a stack structure. When the processor is halted, the resultant execution history can be read back by the MetaWare® debugger via the SoC's JTAG port: no special interfaces or external hardware are required.



Highlights & Key Features

Highlights
Highlights + -

  • Spots Hard-To-Find Bugs
    • Synopsys SmaRT records actual instruction locations and makes them available via the MetaWare Debugger. The ability to trace the exact execution path allows engineers to identify and correct the toughest of bugs.
  • Minimal Area and Power Penalty
    • Synopsys SmaRT tracing can be disabled in normal operation, reducing its impact in terms of power consumption to effectively zero. It requires less than 8.5 k gates to implement, so the cost in silicon area is low.
    • Synopsys SmaRT tracing uses the SoC's existing JTAG port, so it requires no addtional interface circuitry.
  • Easy To Integrate
    • Synopsys SmaRT is supplied as a hardware IP block that can be included on-chip by a designer using the Synopsys ARChitect processor configurator. Using this GUI-based design tool allows SmaRT to be configured for use within devices based on any Synopsys ARC core.
  • Easy To Use
    • SmaRT is designed for use in conjunction with the MetaWare Debugger. The debugger can be used to switch Synopsys SmaRT tracing on and off as part of normal program execution, by setting a control bit.
    • Trace results can be displayed in an intuitive fashion, along with other program information available to the debugger.

    • Product Details

    Resources

    Find Your IP

    Search for IP

    Quickly identify and access the right IP solutions for your project needs.


    Foundation IP Selector

    Find embedded memory and logic IP for your SoC design.

    Explore

    Non-Volatile Memory IP Selector

    Find silicon-proven NVM IP for your SoC design needs.

    Explore