Synopsys ARC µDMA Option for EM Processors

A DMA controller improves efficiency by moving data around in a system without the involvement of the CPU. The µDMA controller is a fast, low energy optimized option for Synopsys ARC® EM Processors to allow fast DMA transfers with low gate count and low power consumption. The µDMA engine is tightly coupled to the EM core interfaces to achieve low latency and cycle-efficient DMA transfers optimized to reduce energy. The closely coupled memory (CCM) interface supports DMA data transfer to and from ICCM0, ICCM1, DCCM or XY Memory, and a DMA peripheral interface is provided to allow external devices (such as a Synopsys I²C peripheral IP) to initiate DMA transfers. Each channel is assigned a separate request/acknowledge signal interface.