Debug Options for ARC Cores

Real-time Instruction and Data Tracing for ARCv2 ISA-based Cores

Supports ARC EM, ARC HS, ARC VPX, and ARC EV Processor Cores

The Synopsys ARC® Real-Time Trace (RTT) unit is a hardware module that provides a real-time tracing capability that helps trace executed instructions or program flow and data. It provides an added dimension to aid debugging of Synopsys ARC processors that are based on the ARCv2 instruction-set architecture (ISA). ARC RTT generates Nexus 5001 class 3-compliant trace messages. It supports real-time instruction and data tracing for all members of the ARC EM, ARC HS, ARC VPX, and ARC EV processor families. ARC RTT is compatible with the ARC MetaWare, the Ashling Vitra-XS Debug & Trace Probe and Lauterbach TRACE32 debuggers.

The ARC RTT supports single- and multi-core ARCv2 implementations, up to a maximum of four processors. The RTT system can be set up in many different configurations, which need to be specified as build-time configurations by including the trace generator in the core and the RTT module at build time. Everything is then automatically handled by the ARChitect tool. ARC RTT can support on- and off-chip memory setups to suit your application tracing needs.

Small Rapid Program Tracing Module Spots Hard-To-Find Bugs

Supports ARC EM, HS, 700 and 600 Cores

Synopsys' Small Real-Time Trace (SmaRT) is a hardware module that can be integrated into any system-on-chip (SoC) within the Synopsys ARC configurable architecture. Delivered via the Synopsys ARChitect configuration tool as an IP library component, it enables rapid software debug with minimal increase in die size and little power consumption penalty.

SmaRT gives developers the ability to trace program execution precisely in the real system. They can therefore diagnose bugs that are difficult to reproduce in system simulators, or only become apparent when the system is run at full speed.

The system works by recognizing any change of program flow control: the relevant source and destination instruction addresses are then recorded within a stack structure. When the processor is halted, the resultant execution history can be read back by the MetaWare debugger via the SoC's JTAG port: no special interfaces or external hardware are required.