EDA
System
IP
SolvNetPlus
Training & Education
Today’s complex automotive applications require robust safety related hardware and software to meet the increasingly stringent automotive safety requirements defined by the ISO 26262 standard. This combination of safety mechanisms provides building blocks for the underlying safety infrastructure at the SoC level.
Many software components are required for customers to build their safety critical solutions. From a basic certified runtime library to a software test library necessary to achieve ASIL certification levels where redundant hardware is not present, to a set of components required to manage SoC level safety escalations, diagnostic error injection, test execution and fault detection time intervals (among other functions), Synopsys provides a comprehensive software offering.
The functional safety (FuSa) software components in conjunction with Synopsys’ ASIL certified MetaWare Development Tools for Safety and industry leading ARC® FS processors provide comprehensive ASIL compliant solutions which dramatically reduce customers’ risk and SoC certification effort.
The FuSa software portfolio supports of a number of software components:
- Synopsys ARC Safety Management Library comprising test, fault, and watchdog manager units, example MCAL layer code and complex drivers to ease AUTOSAR integration
- Synopsys ARC Software Test Library (STL) implements an external software safety mechanism for ASIL certification where redundant hardware is not present
- Synopsys ARC FuSa C runtime library building blocks for safety-critical applications
ARC Functional Safety Software
Read the Software Self-test as a Safety Mechanism for Processing Units White Paper to learn more about Synopsys ARC Software Test Library.
Highlights & Key Features
- Synopsys ARC Software Test Library (STL)
- ASIL-D certified software that implements external software-based hardware safety mechanism provided for EM22FS, HS4xFS, EV7xFS, VPX5FS processors
- Designed together with HW safety mechanisms to meet ASIL B requirements for non-lockstep cores with minimal extra HW and minimal SW overhead
- Made according to state-of-the-art SPFM proving process built with Synopsys EDA tools and matching ISO26262:2018 criteria
Product Details
Find Your IP
Search for IP
Quickly identify and access the right IP solutions for your project needs.
Foundation IP Selector
Find embedded memory and logic IP for your SoC design.
Non-Volatile Memory IP Selector
Find silicon-proven NVM IP for your SoC design needs.