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The Synopsys ARC® EM4 and EM6 processors are optimized for use in embedded and deeply embedded applications where high performance with minimum power consumption is essential. The cores offer outstanding performance density, delivering 1.81 DMIPS/MHz and 4.18 CoreMark/MHz within a very small footprint and extremely low power consumption.
The Synopsys ARC EM4 and EM6 processors are based on the ARCv2 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density.
Both the ARC EM4 and EM6 support up to 2MB of closely coupled memory and are ideal for embedded applications in consumer, IoT, networking, automotive and other power- and cost-sensitive applications. The ARC EM6 processor also supports up to 64KB of instruction and data cache.
Figure 1: Synopsys ARC EM4 and EM6 Block Diagram
Register for the ARC EM Processor Online Training
Highlights & Key Features
- Very small size - 0.01mm2 (28 HPM)
- 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
- Up to 240 interrupts with 16 levels
- 512B - 2MB instruction closely coupled memory (ICCM)
- 512B - 2MB data closely coupled memory (DCCM)
- Up to 64K instruction and data cache (EM6)
- Native ARM® AMBA® AHB™ and AHB-lite™ bus interfaces
- Optional 32x32 or 16x16 multipliers, or both
- Support for custom user extensions - APEX technology
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