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The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-time performance is required. The cores offer outstanding performance with a small area footprint and low power consumption.
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 40-bit physical address space and can directly address memories up to 4.5 Petabytes (4.5x1015) in size. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with support for up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
Highlights & Key Features
- Dual-issue, 32-bit processors for high-performance real-time applications
- Multicore Processor versions with up to 16 CPU cores and up to 16 hardware accelerators
- Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
- Real-time enhanced virtualization
- High degree of configurability
- Support for custom instructions
- Support for up to 16 MB of closely coupled memory and direct mapping of peripherals
- Optional MMU with hardware page table walk and up to 16 MB page sizes
- Optional support for RISC-V defined vector extensions (RVV)
- Real-time Trace (RTT) provides real-time trace debugging features
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