Taking the Risk out of Developing Your Own RISC-V Processor with Fast Architecture-Driven PPA Optimization

The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and microarchitectural extensions to differentiate designs across application areas including AI, machine learning, automotive, data center, mobile, and consumer. Traditionally, designing proprietary cores with the right extensions has been challenging given the high degree of complexity and the high level of expertise required. Evaluating the impact of design decisions on power, performance and area (PPA) can pose a significant hurdle.

This webinar will cover two products from Synopsys’ portfolio of industry leading tools: Synopsys ASIP Designer and Synopsys RTL Synopsys Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved.