Efficient Dual Core LockStep Processor Design with ASIP Designer: An ST STxP5 Case Study

To face increasing demand in SoCs for Functional Safety and Security, ST is developing custom processors implementing mechanisms that satisfy ISO26262 safety requirements and protect program execution against physical attacks. 

In order to reduce the risk due to random faults and thus achieve high safety integrity, or to protect against physical attacks, logic duplication also called Dual Core LockStep (DCLS) is a commonly deployed method. 

ST’s proprietary core is developed using Synopsys’s ASIP Designer tool which allows to capture its ISA, architecture & microarchitecture and generate the RTL of the core in an efficient manner, next to the generation of an optimizing C compiler and instruction set simulator. 

To increase the efficiency of the DCLS design, ST has worked with the Synopsys ASIP team, specifying a new RTL generation option which duplicates the core and generates duplicated monitors in an automatic way. Specific ST tool feature requests were implemented aiming at increasing the functional safety and security goals of the DCLS design. 

This presentation will explain how and why ST involved the Synopsys ASIP team in the development of this solution, and it will describe the process to generate the DCLS and its design results.


Anne Merlande

Senior Member of Technical Staff

Processor Architect and Designer

Computing and Compiler Center


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