2024-08-19 01:01:11
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications requiring high-bandwidth HBM3 DRAM interfaces operating at up to 9600 Mbps. The Synopsys HBM3 PHY offers superior power efficiency compared to any other off-chip memory interface and supports up to 4 active operating states enabling dynamic frequency scaling. To minimize area, the PHY utilizes an optimized micro bump array. Support for longer channel lengths allows more flexibility in the PHY placement on the SoC without impacting performance. The PHY provides a complete HBM3 interface solution when combined with Synopsys HBM3 Controller IP and HBM3 memory model VIP.
The configurable Synopsys HBM3 PHY is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated application-specific HBM3 I/Os required for HBM3 signaling. The design is
optimized for high performance, low latency, low area, low power, and ease of integration. The hard macrocells are easily assembled into a complete 1024-bit HBM3 PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configuration registers, and BIST control. The HBM3 PHY includes a DFI 5.0-compatible interface to the memory controller, supporting DFI DFI 1:1:2, DFI 1:2:4 and DFI 1:4:8 clock ratios. The design is compatible with both metal-insulator-metal (MIM) and non-MIM power decoupling strategies. Synopsys also offers a pre-hardened “drop-in” version of the Synopsys HBM3 PHY for customers who do not have significant custom requirements. For customers that require a custom hard Synopsys HBM3 PHY, Synopsys also offers PHY hardening design services.
Synopsys HBM3 PHY Datasheet
Highlights
Products
Downloads and Documentation
- Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
- 16 independent 64-bit memory channels
- Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
- Supports up to 4 trained frequencies with <5us switching time
- DFI 5.0-compatible controller interface
- PHY independent training capability
- Comprehensive set of design-for-test (DFT) features
Description: |
HBM3 PHY (Hard 1) - TSMC N5 |
Name: |
dwc_hbm3_phy_hard1_tsmc5ff12 |
Version: |
1.20a-EWHardened |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP HBM3 Programming Guide (Document Version: 1.41a) ( PDF | HTML )
Synopsys PHY IP HBM3 TSMC CoWoS-S Interposer Design Guidelines using 3DIC-Compiler (Version 1.00a) ( PDF | HTML )
Synopsys PHY IP HMB3 Signal Integrity and Power Integrity Training Guide (Version: 0.30a) ( PDF | HTML )
Databooks DesignWare Cores HBM3 Hardened PHY for TSMC5FF12 (HIP Version: 1.20a) ( PDF | HTML )
DesignWare Cores HBM3 PHY Utility Block Databook (PUB Version: 1.21a) ( PDF | HTML )
Datasheet Synopsys HBM3 PHY Datasheet ( PDF )
Release Notes DesignWare Cores HBM3 Hardened PHY Release Notes for TSMC5FF12 (HIP Version: 1.20a) ( TEXT )
|
Download: |
dwc_hbm3_phy_hard1_tsmc5ff12 |
Product Code: |
F857-0, H347-0 |
Description: |
HBM3 PHY - TSMC N5 1.2V |
Name: |
dwc_hbm3_phy_tsmc5ff12 |
Version: |
1.24a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP HBM3 Programming Guide (Document Version: 1.41a) ( PDF | HTML )
Synopsys PHY IP HBM3 TSMC CoWoS-S Interposer Design Guidelines using 3DIC-Compiler (Version 1.00a) ( PDF | HTML )
Synopsys PHY IP HMB3 Signal Integrity and Power Integrity Training Guide (Version: 0.30a) ( PDF | HTML )
Databooks DesignWare Cores HBM3 PHY Databook for TSMC5FF12 (PHY Version: 1.24a) ( PDF | HTML )
DesignWare Cores HBM3 PHY Utility Block Databook (PUB Version: 1.21a) ( PDF | HTML )
Datasheet Synopsys HBM3 PHY Datasheet ( PDF )
Implementation Guide DesignWare Cores HBM3 PHY Implementation Guide (Document Version: 1.50a_d1) ( PDF | HTML )
Release Notes DesignWare Cores HBM3 PHY Release Notes for TSMC5FF12 (PHY Version: 1.24a) ( TEXT )
|
Download: |
dwc_hbm3_phy_tsmc5ff12 |
Product Code: |
F026-0, H334-0 |
Description: |
HBM3 PHY - TSMC N6 |
Name: |
dwc_hbm3_phy_tsmc6ff18 |
Version: |
2.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP HBM3 Programming Guide (Document Version: 1.41a) ( PDF | HTML )
Synopsys PHY IP HBM3 TSMC CoWoS-S Interposer Design Guidelines using 3DIC-Compiler (Version 1.00a) ( PDF | HTML )
Synopsys PHY IP HMB3 Signal Integrity and Power Integrity Training Guide (Version: 0.30a) ( PDF | HTML )
Databooks Synopsys PHY IP HBM3 PHY Utility Block Databook (PUB Version: 2.00a_OD) ( PDF | HTML )
Synopsys PHY IP High Bandwidth Memory (HBM3) PHY for TSMC6FF18 (PHY Version: 2.10a) ( PDF | HTML )
Implementation Guide DesignWare Cores HBM3 PHY Implementation Guide (Document Version: 1.50a_d1) ( PDF )
Release Notes Synopsys PHY IP High Bandwidth Memory (HBM3) PHY for TSMC6FF18 Release Notes (PHY Version: 2.10a) ( TEXT )
|
Download: |
dwc_hbm3_phy_tsmc6ff18 |
Product Code: |
H757-0 |
Description: |
HBM3 PHY V2 - TSMC N3E |
Name: |
dwc_hbm3_phy_v2_tsmc3eff12 |
Version: |
1.11a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP High Bandwidth Memory (HBM3 V2) PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY Programming Guide (Version 1.40a) ( PDF | HTML )
Databooks DesignWare Cores HBM3 V2 SDRAM PHY Utility Block (PUB) Databook (Version 1.20a) ( PDF | HTML )
Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY for TSMC3eFF12 Databook (PHY Version: 1.11a) ( PDF | HTML )
Release Notes Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY for TSMC3eFF12 Release Notes (PHY Version: 1.11a) ( TEXT )
|
Download: |
dwc_hbm3_phy_v2_tsmc3eff12 |
Product Code: |
F854-0, H748-0 |
Description: |
HBM3 PHY V2 - TSMC N5 |
Name: |
dwc_hbm3_phy_v2_tsmc5ff12 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes Synopsys PHY IP High Bandwidth Memory (HBM3 V2) PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY Programming Guide (Version 1.40a) ( PDF | HTML )
Databooks DesignWare Cores HBM3 V2 SDRAM PHY Utility Block (PUB) Databook (Version 1.20a) ( PDF | HTML )
Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY for TSMC5FF12 Databook (PHY Version: 1.00a) ( PDF | HTML )
Release Notes Synopsys PHY IP High Bandwidth Memory (HBM3) V2 PHY for TSMC5FF12 Release Notes (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_hbm3_phy_v2_tsmc5ff12 |
Product Code: |
I668-0 |