Early Architecture Performance and Power Analysis of Multi-Die Designs

Despite the clear advantages of multi-die designs, there are numerous new challenges that stand in the way of multi-die design realization. This white paper focuses on those challenges that can be addressed by early architecture exploration of multi-die designs, including:

• System pathfinding
• Memory utilization and coherency
• Power/thermal management

Find out how to overcome such challenges with Synopsys Platform Architect for Multi-Die, a SystemC™ standards-based performance and power analysis tool for early architecture exploration of multi-die designs. It accounts for the interdependencies between multiple dies (also referred to as chiplets) within multi-die systems. Platform Architect for Multi-Die helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power under consideration of the die-to-die interfaces. The solution includes a die-to-die model, including UCIe, as part of its library portfolio to compose a multi-die system for early architecture exploration.