In our data-driven world, applications like high-performance computing (HPC) and artificial intelligence (AI) are taking center stage, delivering intelligence and insights that are transforming our lives. However, the growing complexities of HPC and AI designs are driving the need for much more complex semiconductor devices. Increasingly, multiple components and technologies are coming together in hyper-convergent designs to meet demands for bandwidth, performance, and power for these compute-intensive applications. To achieve power, performance, and area (PPA) targets, such complex chips need to be analyzed as a single system—an approach that’s difficult to support via traditionally disparate tools. In this blog post, we’ll examine the trend of IC hyperconvergence and explain why the traditional, disaggregated approach to circuit simulation is no longer sufficient.
What is IC hyperconvergence? Simply put, a hyper-convergent IC design is one that is comprised of disparate components integrated on the same die or the same package. It’s like our familiar system-on-chip—but packed with a lot more functionality. A single die or package, for instance, can feature a diverse set of analog, digital, and mixed-signal components, some built on different process nodes and catering to a variety of functions. The complexity increases further when the various components are integrated vertically using 2.5D/3D architectures in a system-in-package (SiP).
From technology generation to generation, SoCs have grown more complex with more integration in response to application needs. As recently as 2015, advanced-node SoCs were primarily digital designs, with separate discrete analog components on mature nodes and fairly low data rates for on-chip IO. Fast-forward to 2020 and you’ll have noticed the increasing prevalence of advanced-node SoCs with integrated analog components, larger and faster embedded memory, and complex IOs with 100+ Gb data rates. And today, we’re seeing the emergence of high-bandwidth memory (HBM) designs consisting of large 3D stacked DRAM integrated with the SoC on a 3DIC or in a SiP.
While today’s highly integrated designs provide a way for designers to stretch the limits of Moore’s Law, the evolution also points to increased scale complexity and system complexity. From a scale standpoint, we’re seeing reduced margins and increased parasitics in advanced nodes. Also, larger and more complex circuits demand higher quality of results (QoR), time-to-results, and cost-of-results. On the system side, complex multi-function and multi-technology silicon integrations are driving designers’ need for unified workflows around a common circuit simulation solution. In other words, the disparate tools that we’ve long been accustomed to are not adequate to meet the evolving needs in this environment.