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Introduction
Sony Semiconductor Solutions Corporation is a global leader in the design and production of semiconductors, with image sensors as its flagship product. As the world’s top supplier, its vision is to remain indispensable by providing cutting-edge imaging and sensing solutions for both individual enjoyment and societal safety.
Challenges in Image Sensor Layout Design
Modern CMOS image sensors often employ a stacked architecture, with mixed-signal chips featuring numerous analog macros. Routing between these macros faces strict constraints: parasitic resistance, total capacitance, and coupling capacitance must all be tightly controlled. Traditionally, our designers manually laid out thousands of inter-macro wires—70% digital and 30% analog and power lines. This manual process, while precise, was time-consuming and presented significant efficiency challenges. Our initial goal was to reduce the workload for draft layout and initial routing by 10% through automation.
At SNUG Japan 2025, Akihiro Maeda talked about their solution for image sensor layout design and further challenges.
Transition to Co-Design Flow
To address these challenges, Sony adopted the Co-Design flow from Synopsys, which enables seamless interaction between Fusion Compiler and Custom Compiler using the ndm format. Previously, manual analog routing and digital block creation were performed separately, followed by integration and verification. With Co-Design, the entire chip is built as a single ndm design, allowing designers to switch between manual routing (Custom Compiler) and automated routing (Fusion Compiler) as needed.
Results and Key Functions Developed
Implementing the Co-Design flow allowed Sony to automate nearly all digital routing. Real-time quality checks within Fusion Compiler replaced the previous need for separate RC extraction and timing analysis after integration. However, automating analog routing was more complex due to the need for intricate patterns, shield routing for low coupling, and the simultaneous layout of competing requirements. Single-wire automation worked, but scaling up increased preparation time, and some automated results lacked the finesse of manual design.
To balance automation and quality, Sony selectively automated specific routing steps and focused on overall workload reduction, including verification. Four key functions were developed to support this effort:
- Automatic Power Mesh Generation: Using Custom Compiler, designers can generate mesh patterns with customizable layers and pitch, avoiding blockages and ensuring optimal power delivery. By defining mesh regions, resistance between points can be estimated using pre-calculated sheet resistance, enabling designers to iteratively refine mesh shapes and trim them once resistance targets are satisfied. Standardizing mesh patterns enables highly predictable results and halves layout time compared to manual methods.
- Automated Shield Generation: While full analog routing automation remains challenging, shield shapes can be generated automatically. Complex low-resistance routes are grouped as “bunch_net,” preventing accidental shield insertion and reducing excessive checks. Designers input shield parameters, and the tool generates shields for multi-layer routes with one click. Registering variations and rules further streamlines the process, cutting shield generation time by half.
- Shield Check Function: To meet stringent constraints on coupling capacitance, missing shield protection must be quickly identified and corrected. Custom Compiler’s shield check function finds issues such as incomplete shields or incorrect net names—cases that are difficult to spot visually. This function integrates with the shield automation workflow, requiring no extra constraints if shield generation is used.
- Point-to-Point Resistance Extraction Interface: For verification, designers specify pin names for points to be measured. The tool automatically retrieves coordinates, links to the GUI for cross-probing, checks physical connectivity, and verifies resistance against constraints. Violations are instantly flagged for correction. Though user-custom functions were initially implemented with Tcl, Custom Compiler now supports Python and Copilot, making such functions easier to create.
Summary and Ongoing Challenges
Transitioning to the Co-Design environment enabled full automation of digital routing and partial automation of analog and power routing. Verification became more efficient with checks for shield implementation issues and point-to-point resistance extraction.
However, further gains are possible. Most of the remaining workload involves manual routing, which could be reduced by expanding tool-manageable constraints and by visualizing the tacit “beautiful routing” standards held by expert designers.
The transition also introduced new challenges, especially in managing digital design constraints such as Liberty files and SDCs. Area control is another issue. Now that both manual and automated routing tools are available, it is crucial to define which regions use each method and to reflect the results in blockages. Sony is collaborating with Synopsys to develop a streamlined flow for this process.
Future Expectations for Synopsys
Looking ahead, Sony hopes Synopsys will address several key needs:
- Collaborative Design: A flow that allows multiple designers to simultaneously edit different areas of the same logical hierarchy, with each designer’s changes reflected to others in real time, or at least within an environment that supports area extraction and later integration into master data.
- Capacitance-Driven Layout: The Auto Router should directly accommodate capacitance constraints, including both total and coupling capacitance. It should also automatically resolve trade-offs with other wiring to ensure compliance.
- Scalability and Performance: Even for large designs with many instances, fast drawing and responsive tools are expected.
- Integration of .da and .ai: Current .ai tools operate only on explicit constraints, while manual routing relies heavily on tacit ones. If .da tools can analyze and learn these implicit standards, and .ai tools can apply them, it would greatly enhance automation. Linking these results to Silicon.da would be even more beneficial.
Conclusion
The Co-Design approach has served as an example of how collaboration between design methodology and advanced EDA technology can contribute to improvements in the efficiency and quality of image sensor design. We deeply appreciate Synopsys’s support in implementing this flow and in developing new features beyond the scope of this article.
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