AI-based design optimization: Once the design was migrated to 5nm, we used Synopsys PrimeWave AI-based design optimization solution to center the design across all 360 PVT corners and multiple tests.
Based on the designer’s input, a set of devices and device parameters was chosen for the optimizer to manipulate, and the bandgap specification will be used as matrices to achieve. Parasitic data from the migrated layout can be added for the optimizer to consider as part of its job.
The results: Design optimization that completed in hours versus in days.
The bandgap design was optimized across all 360 PVT corners in under three hours. The turnaround time (TAT) benefit is obvious: getting a task done in a few hours versus days provided a substantial productivity boost and resulted in superior design results.
Layout Migration Details and Post-Layout Verifications
The bandgap circuit has very strict requirements for matching. Using the migrated schematics and topologies and the layout structures that were extracted from the bandgap design in 14nm node, we were able to truly migrate (not simply regenerate) the layout at the new 5nm node. Custom Compiler was able to detect and “learn” analog placement and matching patterns for the FinFET transistors, resistors, capacitors banks, and bipolar devices. The placement and the routing engines were tuned to “learn” and follow the original topologies that were present in the original 14nm layout. Dummy devices, guard rings, and tap cells were added to comply with the 5nm design rules.
As part of this exercise, we migrated the 14nm bandgap design to both 8nm and 5nm nodes. As you can see from the picture below, the placement and layout topology looking very similar in all three layouts.