Toshiba Enhances Memory BIST Flow with Synopsys TestMAX Manager

Each year, SNUG Japan brings together semiconductor and system design engineers to share practical learnings, workflows, and best practices across the Synopsys ecosystem.  In a presentation at SNUG Japan 2025, Toshiba Electronic Devices & Storage Corporation shared progress in advancing memory BIST automation and diagnosis using TestMAX™ Manager and an in-house library development effort.

Shinya Fujita, Toshiba Electronic Devices & Storage Corporation reported significant advancements in its Memory BIST (Built-In Self-Test) flow through the adoption of Synopsys’ TestMAX Manager and the development of an in-house memory library. This initiative addresses long-standing challenges in test automation, tool integration, and memory diagnosis, reflecting Toshiba’s commitment to quality and innovation in the semiconductor industry. 

The evaluation used TestMAX Manager, Embed-It Test, and TestMAX Advisor (all version 2025.06), verifying top-down insertion/validation, RTL editing, SMS implementation using in-house memory, manufacturing test pattern generation and verification, and diagnosis flow. All basic functions were successfully confirmed, resolving issues encountered in previous flows.

Several challenges were identified in the earlier SMS flow:

1. Tool Proficiency: The previous process required engineers to master different tools for generation, insertion, and verification, with no integrated clock or connectivity checks.
2. Manual Operations: Frequent manual intervention was necessary to resolve unconnected signals during MBIST insertion. There was no RTL editing function, and additional cell insertion required separate tools. Multiple instantiations of modules could lead to redundant processor insertions, necessitating prior RTL uniquification.
3. Verification/Test Time: Strict clock constraints (BIST clock required to be eight times faster than TCK) increased verification and test time.
4. In-House Memory Library Construction: The existing infrastructure lacked automation and flexibility, complicating efficient deployment and diagnosis.

The adoption of TestMAX Manager centralized operations within dft_shell, simplifying configuration and reducing the need to switch between tools. Enhanced automation and bug fixes enabled seamless implementation and verification, and the addition of TestMAX Advisor improved DRC capabilities, including clock tracing and debugging features.

Manual operations were significantly reduced. The modify_rtl function enabled in-tool RTL editing, simplifying the insertion of multiplexers and resolving previous connection issues. Problems with multiple module instances were also addressed, minimizing troubleshooting efforts.

Verification and test time constraints were alleviated through hardware improvements. The BIST clock is now only required to be faster than TCK, eliminating the need to lower TCK and reducing overall test time. However, Toshiba anticipates further enhancements to enable unified clock periods, as supported by some other tools.

Throughout the evaluation, tool-related issues were minimal and largely resolved through sample scripts and support from Synopsys Japan. Toshiba has requested additional tool enhancements, such as allowing instance name specification for memory boundary MUX gates and improved scan bypass cloning avoidance.

A key component of the initiative was the development of the MASIS (Memory and SMS Interface Standard) library, essential for SMS integration. MASIS is used for implementation verification, pattern generation, and fault diagnosis. While MASIS is available from major SRAM vendors, no MASIS exists for Toshiba in-house memories. As a result, Toshiba has developed a MASIS generation and verification environment based on the Synopsys MASIS Compiler. 

One of the main challenges involved deriving bitcell coordinates for fault diagnosis, complicated by “straps” (gaps in bitcell arrays). The lack of fixed rules for straps made investigation and implementation time-consuming and complex for each SRAM configuration.

The introduction of the MASIS Compiler addressed these issues. The development flow now includes template generation with MIGM, strap extraction and verification with MIVM, and logical verification with VrMC. This structured approach enables automated MASIS creation and validation, allowing efficient generation of MASIS libraries for different memory configurations. Physical and logical verification steps ensure alignment between MASIS and GDS layouts, and by applying MASIS to the in-house memory developed this time, we were able to obtain fault diagnosis results, including exact physical coordinates, using the Synopsys Silicon Debugger.

The implementation of TestMAX Manager and related tools has significantly streamlined Toshiba’s MBIST flow, resolving previous challenges and automating many manual processes. The MASIS Compiler has reduced the workload and complexity of in-house memory library development, paving the way for broader adoption. The verification flow—from hardware design to mass production pattern analysis—has been validated, including accurate coordinate display for fault diagnosis.

Looking ahead, Toshiba seeks further enhancements, such as relaxed clock frequency constraints and more flexible instance naming for memory boundary MUX gates, to further boost productivity and design flexibility. The company plans to apply these solutions in upcoming product development cycles and continues to seek support for ongoing verification and methodology advancements.

To learn more about the capabilities discussed here—top-down MBIST insertion/validation, RTL edit support, and diagnosis—explore the Synopsys TestMAX family and reach out for more details.