How Chip Floorplan Design Automation Accelerates Chip Design

Preeti Jain

Jun 06, 2022 / 6 min read

Chip designers understand how important floorplanning is to quality placement and routing (P&R), and quality P&R leads to successful chip design closure. Floorplan design, however, is time-consuming and tedious. Emerging verticals such as artificial intelligence (AI), high-performance computing (HPC), and hyperscale data centers are leading to increased chip design complexity and unique architectural challenges.

With growing design size and complexity, the number of macros in a design is also rapidly increasing. As a result, floorplanning design is dominating project schedules, and designers are looking for ways to meet their aggressive quality-of-results (QoR) goals with a reduced number of floorplan iterations.

There’s now a solution to this inevitable challenge: a technology that automates floorplan design, saving days to weeks, and sometimes even months, of effort. In this blog post, I’ll discuss the newest capabilities of the Synopsys IC Compiler™ II and Synopsys Fusion Compiler™ P&R solutions, which bring automation and intelligence to the equation. As an example, I’ll highlight how Global Unichip Corp. (GUC) has deployed FreeForm Macro Placement technology available in both tools to accelerate the path toward better quality-of-results compared to a traditional, manual process.

ASIC (Abstract)

What Makes Traditional Floorplanning Time-Consuming and Tedious?

Traditionally, floorplanning—the placement of an IC’s major functional blocks, or macros—entails manual trial and error to uncover a good data flow for the chip. Once the macros have been placed, the remaining space is devoted to the standard cells. The goal is to place each block in a manner that generates the power, performance, and area (PPA) targets established for the design at hand. If you’re working on a design type that’s familiar to you, you might be able to rely on your experience and some institutional knowledge to speed up the process. For example, perhaps you’re a wiz at SoCs for HPC designs, so you have a sense for how to place and route the chip to extract the performance needed while minimizing power consumption. But when there are as many as thousands of macros, well, there are limits to how quickly manual efforts can move.

Floorplan design iterations can span from days to weeks depending on the size and complexity of the chip. When done by hand or with existing, traditional floorplanning solutions, designers are limited to placing macros at the edges of the block. But this isn’t always ideal, as it can result in blockages and/or sub-optimal quality.

GUC, an advanced ASIC leader that provides IC implementation and SoC manufacturing services, has successfully used Synopsys’ digital implementation flow for many years, including at advanced nodes such as 3nm and 5nm. Based in Taiwan, the company has demonstrated its value in maximizing power and performance while delivering the fastest time-to-market possible for its customers. In order to continue meeting and exceeding its customer requirements, GUC needed to streamline the design cycles for its AI, HPC, mobile, automotive, and IoT designs. The company needed a solution to increase P&R productivity as, with 2000+ memories in their complex SoCs, floorplan design was becoming a big challenge.

This image shows 2000+ macros in one of GUC’s complex SoCs.

Increasing P&R Productivity with FreeForm Macro Placement

In a presentation at SNUG Taiwan, GUC discussed its floorplanning benchmark and successful tapeout using Synopsys IC Compiler II for their large 12nm HPC chip. They demonstrated how FreeForm Macro Placement technology played an instrumental role in significantly reducing floorplan design time and accelerated their tapeout schedule by months. In its experiment, the team performed two parallel runs with the same P&R flow. In one instance, they did floorplanning using the traditional iterative process and used Synopsys IC Compiler II to complete the rest of the P&R flow. In the second instance, the team used Synopsys IC Compiler II FreeForm Macro Placement to automate the floorplanning part of the process. The connectivity-driven FreeForm Macro Placement technology is congestion-aware and simultaneously places standard cells and macros for better quality-of-results (QoR). Its coarse placement engine concurrently optimizes wirelength, timing, and power for macros and standard cells.

Comparing the two runs, GUC found improved PPA results with the single-pass second run using the FreeForm Macro Placement technology:

  • 14% reduced switching power and 19% wirelength reduction
  • Lower leakage power due to a better VT ratio
  • Lower dynamic power due to a better total net length/cap
  • Zero glitch violations, resulting in better signal integrity (SI) because of a shorter memory-to-logic path
Manual SoC Floorplan | Synopsys

The image on the left shows the results using traditional, manual floorplanning, while the image on the right is the outcome after applying FreeForm Macro Placement technology.

“Overall, the results we experienced using Synopsys IC Compiler II FreeForm Macro Placement gave us a dramatic reduction in floorplan design time, to meet our aggressive ASIC design creation schedules with best-in-class PPA metrics,” said Louis Lin, senior vice president at GUC. “Being able to reduce floorplan iterations while still achieving optimal timing and congestion enables us to help our customers accomplish their product delivery objectives for demanding designs in areas like next-generation AI hardware, HPC, automotive, mobile, and the IoT.”

Optimizing Floorplan by Applying Machine Learning to Macro Placement

In addition to the FreeForm Macro Placement technology, Synopsys IC Compiler II has also been enhanced with a next-generation Machine Learning-Driven Macro Placement technology. The machine learning- (ML-) based technology leverages the powerful coarse placement engine and predicts the QoR of macro cell placement based on data collected from previous results, creating the most optimal out-of-the-box macro placement for congestion and timing. The technology predicts congestion, wirelength, and total negative slack (TNS) and significantly reduces manual tuning efforts. By automatically exploring hundreds of floorplans on-the-fly, the technology can generate the top-performing floorplan output.

ML models are trained along the way, and the more data available for the training, the smarter the technology becomes over time. Given the vast exploration space in an IC, particularly AI architectures that commonly boast thousands of macros, ML techniques are well suited to address the challenges of floorplan design. ML data, from both users and the factory ML data library in the tool, is saved for reuse by other designs.

Synopsys IC Compiler II and Synopsys Fusion Compiler are part of the Synopsys Digital Design Family, the industry’s first AI-enhanced, cloud-ready design solution set that redefines conventional EDA tool boundaries across synthesis, P&R, and signoff. The comprehensive platform is geared toward delivering optimal PPA and time-to-results. The company has also integrated various Synopsys IP into its solutions.


The floorplan for a chip maps out where all of the essential components go. Ideally, the macros and standard cells should support a good data flow for the chip, in order to generate the best PPA for your target application. Traditionally, floorplanning has been a manual, time-consuming process. New automated and machine learning-driven technologies in Synopsys IC Compiler II and Synopsys Fusion Compiler digital implementation solutions streamline floorplan design for better results and productivity. GUC, for example, achieved a 14% reduction in switching power and a 19% reduction in wirelength using the FreeForm Macro Placement feature in Synopsys IC Compiler II.

Using the latest floorplanning technology designed with automation and intelligence can generate both the quality and the timeframe that your designs demand.

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