With all these exciting new applications and current needs to address the increased bandwidth for stay-at-home workers come design challenges for the engineers that design the silicon powering HPC and cloud technologies. Here are some of the top design challenges that engineers will face next year and beyond.
“Because a lot of data is stored in centralized compute farms today and probably will be even into 2021, it is susceptible to attack. Hackers know where the information is because it’s not spread out across a million devices, so security is going to be a big issue for both hardware and software. That’s why Synopsys is working with government agencies like DARPA to ensure secure hardware design, which will eventually be utilized in more consumer-focused industries such as banking that have a big need for security,” said Molina. “Chips are going to get bigger and they’re going to require more performance. There are a couple of things that can potentially limit that; one is, how much logic can you possibly fit on one die, and the other is, how do we design things of that scale? To help overcome design scale on a single die, designers are looking at 3DIC which disaggregates design into multiple integrated chip designs. This means that from the very beginning, designers will need to do even more early floor planning and package-based signal integrity analysis using tools like Synopsys’ 3DIC Compiler. In terms of handing growing single die design sizes, designers need tools like the Fusion Compiler that allow them to operate on an ever-increasing number of compute cores, which lends itself to usage in a cloud environment. In a cloud environment, you have access to literally thousands of compute resources. If your tools aren’t set up to be able to run across all of those compute resources, their value to designers will be limited from an overall performance and time-to-market standpoint.”
“We’re seeing silicon geometries continue to shrink, which creates both challenges and opportunities. These reduced geometries come with a cost, so striking a balance that will yield an economic benefit as well as implementing these new architectures in such a way that they can get the most impact from development effort is going to be an ongoing challenge,” said Durrant.
“There are new technologies that have been brought forward to address the massive amount of data transfer that’s happening in AI applications for actions like image recognition, such as Compute Express Link (CXL). While in the past, you would have to transfer all the data from the memory, we’re going to see more use of cache coherent technology to leave most of the data in its original location to work on and only transfer the data that’s absolutely necessary. This will increase the bandwidth of these connections on one hand, while also reducing the amount of traffic that’s going across that same channel to improve the overall performance,” said Knowlton.
“HPC silicon is getting more complex with chips exceeding 10BG in size, along with multi-die and chiplet architectures. Chiplets, which allow designers to mix and match IPs from different versions/generations, pose an integration challenge. IP verification is not just a block-level exercise anymore; it’s verifying the IP in a system context (e.g., IP sees real-world stimulus early on). System-level hardware and software verification will become even more important as we bring up software on these chiplet/multi-die platforms. The number of microcontrollers and firmware sitting in these platforms that need to work together to get to, for example, a system boot is quite challenging. Hybrid engine solutions are a clear way to approach this. This also leads to system-level debug and performance challenges when designers need to analyze and understand system and workload behaviors across multiple levels of abstraction (i.e., OS, driver, firmware, hardware interface, busses, etc.). Another area of importance is early power analysis and estimation; any slight saving on power is monumental for large designs. Synopsys is working along with chip manufacturers to help solve these verification challenges,” said Tadikonda.
Stay tuned for upcoming predictions posts that will outline our 2021 predictions for artificial intelligence (AI), low power, and automotive.