EDA
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Introduction
When we first launched Synopsys Cloud four years ago, one of the key capabilities we wanted to build into the SaaS offering was to enable designers to jumpstart a complete RTL2GDS digital EDA flow as a ready to use preconfigured option with curated compute options and well-defined scripts. Our goal was to help designers save time and start focusing on running their jobs ASAP. Digital Instance 2.0 is a highly evolved release of the original concept with over three years of enhancements based on feedback from engineers and CAD teams from across the semiconductor user base.
The primary problem we are trying to address with this unique solution is to enable engineers to turn design concepts into silicon quickly, with the goal to achieve first-pass silicon success and save months of time to tapeout.
The Challenges of Establishing Efficient Digital Design Flows
As EDA tools continue to evolve with updated options and features to address design complexities, extracting the best PPA (Performance, Power, Area) demands deep expertise and time investment. Today’s SoCs integrate dozens of IPs, each requiring unique recipe tuning. Large design houses rely on dedicated CAD teams to master tool manuals, build scripts, and maintain flows that run into hundreds to thousands of lines of code.
As a startup building their first prototype, or a new design team enabling their first digital project, having a dedicated CAD team might be a luxury. So, designers end up spending precious time setting up flows instead of optimizing designs, slowing productivity, and time-to-tapeout. Some of the most common hurdles faced by engineers include:
Building an effective, scalable CAD environment for end-to-end digital flow that helps engineers deliver quality designs faster.
Ensuring scripts are constantly getting refreshed based on tool updates, technology, and design requirements. With multiple blocks running in parallel, this can become a significant effort and time expenditure for engineers.
Setting up and verifying end-to-end design flows when starting from scratch with no available design flow templates. More importantly, to do this when time-to-tapeout is bound to funding constraints.
Having access to push-button design flows integrated with AI technology to provide more time for thinking through actual design optimizations.
Why Now and What is New in Synopsys Digital Instance 2.0?
Based on over three years of customer feedback from engineers designing AI accelerators and large teams integrating complex SoCs, we revisited the complete digital design flow from RTL to Signoff and thoroughly reviewed to identify and address gaps between various stages.
Some of the key features built into the next iteration of Synopsys Digital Instance include:
Improved correlation and interoperability between tools, eliminating the need for manual intervention by engineering and CAD teams.
Expanded reference scripts for EDA tools used from RTL-to-GDSII stage with ready-to-use RTL-to-Signoff flows able to scale seamlessly from block level to complete SoC including multiple, complex hierarchies
Seamless transfer of settings across tools within the flow.
Automated application of recipes (such as low power optimization, standard cell Vt selections) and defaults to all blocks in chip.
Standardized technology node configurations for quick setup based on Process Design Kits (PDKs) or Foundry Design Kits (FDKs).
Integrated PPA optimization recipes through curated plugins for Arm and other IPs.
Capability to launch and monitor multiple test scenarios on a block or a group of blocks in parallel from a unified execution cockpit.
Built-in support for enabling newer technology nodes and advanced analytics and AI innovations for faster iterations.
These features ensure that outputs from each stage integrate smoothly into the next, eliminating postprocessing burdens for engineering and enabling faster, more predictable convergence.
Built on tool native Reference Methodology (RM) scripts, Digital Instance 2.0 provides access to the latest R&D best practices, tightly integrated within a unified GUI for maximum interoperability.
Below is an architectural block diagram depicting cohesive connections between chip design stages connected with a common GUI based interface and a set of reference methodology scripts. Digital Instance 2.0 makes tight and seamless compatibility between the tools used for RTL-to-Signoff. Engineers can run parts or full RTL-to-Signoff flow. In addition, this setup provides curated services, flows, and PPA recipes to boost productivity and achieve quality results.
Hierarchical Settings for Precise Control
The Digital Instance 2.0 uses a four layer settings architecture, enabling both consistency and flexibility:
Global Layer: Synopsys provided defaults for each tool’s reference methodology.
Technology Layer: Foundry and node specific parameters.
Project Layer: Design level configuration for cross block consistency.
Local Layer: Block specific overrides and custom tuning.
This structure simplifies ownership, improves auditability, and enables rapid PPA exploration across layers, while preserving repeatability.
RTL-to-Signoff Coverage
The platform integrates all major stages, including:
Design Capture
Verification
Implementation
Test & SLM
Signoff
Each stage is connected through a GUI driven cockpit, enabling designers to run individual tasks or full flows with minimal setup.
Example Use Case: Early and Accurate Power Optimization
Power is a critical design metric for modern SoCs. Digital Instance 2.0 enables early RTLlevel power estimation and optimization with strong correlation to implementation, allowing designers to:
Quickly gauge power at RTL and understand trends across revisions.
Evaluate PPA changes efficiently without full implementation cycles.
Use intuitive dashboards to identify high-power modules and weekly trends.
Carry FSDB based switching activity through synthesis and P&R for improved accuracy.
Because settings and constraints stay aligned across RTL, implementation, and signoff, design teams avoid late-stage surprises and reduce iteration loops.
Once Digital Instance 2.0 is set up for your design, alignment of settings (e.g. multi-bit, constant propagation, definition of don’t use cells, etc.), and application of the same design constraints happens out of the box, enabling tight correlation. The same inputs can easily be carried forward through implementation and signoff flows. A complete dashboard of metrics is available to be configured to provide you with precise insights at your fingertips.
Conclusion
Synopsys continues to expand the library of reference scripts for additional tools and add more flows within Digital Instance 2.0 on Synopsys Cloud enabling seamless stitching of design flows, paving the way for integrated yet flexible silicon to system solutions.
The Digital Instance 2.0 is a fully integrated, production ready RTL-to-Signoff solution available on Synopsys Cloud. It is a complete GUI based end-to-end digital design flow, templated for customization and reuse. It enables engineers to jumpstart their design from day one and helps save months of setup and optimization time. It includes quick start kits (QIKs), IP specific curated PPA recipes, and tool native Reference Methodology (RM) scripts also allow teams ranging from startups to full SoC design groups, to deliver high quality designs much faster.
Built under the guidance of an industry expert with over 30 years of CAD experience and enabling 500+ successful chip design tapeouts, Digital Instance 2.0 enables engineering teams ranging from startups to full SoC design groups, to begin design development on day one, with confidence.
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