Taming Advanced Node Physical Verification – NVIDIA’s Perspective

Physical verification presents a particularly difficult problem at advanced nodes. Thanks to an explosion of rules and operations, the traditional and trusted methods of yesterday do not scale to address new requirements. The industry now demands a new and modern software architecture that delivers innovative methodologies. In a prior post on SemiWiki.com, this topic was discussed along with an overview of the fresh approach offered by Synopsys IC Validator™ physical verification signoff solution.

NVIDIA’s results highlight what’s possible when advanced physical verification challenges are addressed with the right architecture and close collaboration. Sudhir Agarwal, Distinguished Engineer at NVIDIA, presented the critical role Synopsys and IC Validator played in their outcomes at the Synopsys Converge event. Here are some details regarding NVIDIA’s perspective on taming advanced node physical verification.

Sudhir Agarwal's team leads physical verification across NVIDIA, supporting everything from day-to-day design iterations to full-chip tapeouts. The team operates across a broad range of design styles and technology transitions, including planar, FinFET, gate-all-around, and multi-die architectures with emerging approaches such as backside power delivery.

As designs scale beyond 100 billion transistors, rule complexity has expanded rapidly, with growing runsets to support edge-based checks, voltage-dependent rules, and other advanced requirements. To manage this complexity, NVIDIA has built a unified physical verification flow that scales seamlessly from standard cells to partitions, chiplets, and full-chip designs.

In the face of this complexity, the physical verification team needs to build a flow that will reliably work on a standard cell, a partition, a chiplet, and a full design in a seamless manner. Sudhir outlined a history of collaboration with Synopsys to achieve seemingly impossible goals.

Sudhir highlighted a 15-year collaboration between NVIDIA and Synopsys that has consistently enabled successful tapeouts. He pointed to close work with Dr. Anil Karanam, who leads the IC Validator R&D organization at Synopsys—an effort that continues to shape the evolution of physical verification.

Sudhir’s experience during this time spans multiple foundries and process nodes. It includes work-in-process and final signoff verification across small cells, blocks, and full chip designs. He made an Important point about NVIDIA’s strategy here. There are many tools available to achieve physical verification across these disciplines.  NVIDIA has found that IC Validator delivers the most efficient and the most reliable results. That is why it’s the tool of choice for all physical verification flows.

Sudhir shared some results for a very large full-chip design. This is one of many large designs NVIDIA tapes out each year. Requirements for this size, leading node GPU design included 24 hours or less turnaround time for full physical verification signoff with optimal compute resource usage. IC Validator delivered these results, signing off DRC, LVS, ANT, and fill less than 24 hours across all flows.  

He also mentioned close collaboration with Synopsys to improve these results further. Sudhir pointed out that even small improvements can have a significant impact due to the size and number of designs being processed. Some very promising improvements as a result if this collaboration are summarized in the table below.

Another successful collaboration focused on compile time improvements. It turns out for many runs compile time is the dominate contributor to overall turnaround time. By focusing on this issue with NVDIA, Synopsys achieved about a 20X improvement. This has a significant impact on overall physical verification throughput. The details of this work are shown in the figure below.

Runtime improvements associated with the NVIDIA Grace™ Arm-based CPU were also reviewed. Sudhir explained that these types of jobs are limited by memory and not CPU throughput. Based on that, Synopsys and NVIDIA optimized design size to achieve an additional 1.6X improvement vs. the X86 architecture, as shown below. 

Sudhir described the tight interaction between the NVIDIA tapeout teams and Synopsys. There is substantial collaboration between these groups. Synopsys rapidly delivers 2-3 new software versions to keep pace with NVIDIA’s requirements during tapeout. NVIDIA has a deep trust in the Synopsys development team – this kind of fast-paced development can only work if that is true.

As discussed, the 15-year collaboration between NVIDIA and Synopsys has consistently enabled successful tapeouts across increasingly complex designs and process nodes. The close partnership with Anil Karanam, who leads the IC Validator R&D organization at Synopsys, continues to drive this work. As part of this collaboration, Synopsys introduced the PXL programmable language to enable flexible, reusable development of complex physical verification runsets. PXL significantly improved configurability and reuse across designs but also introduced additional runtime overhead—particularly for smaller designs running the same checks as large, multi-billion gate designs.

This had become a major challenge for NVIDIA, so Synopsys launched a focused effort, working closely with NVIDIA to find a solution. The project had many goals:

• Faster run set processing
• Enable better optimizations
• Enable better DP scheduling
• Enable better resource management

And most important, optimize large and small design runs with no special settings required. That is, it must deliver the same out-of-box behavior for all designs.

Anil took the stage to describe how Synopsys implemented the project as a collaborative effort with NVIDIA. Due to the robust and flexible nature of the PXL language, running the tool would generate highly complex graphs.

Synopsys developed IGraph (interpreted graph), removing everything except the final polygon checks from the graph. This streamlined graph enables better optimization and resource management, while introducing an elastic mode that allows the tool to scale in and out. The result was a significant improvement in runtime.

The figure below shows the dramatic reduction in both compile and runtime that was achieved with IGraph across several smaller design examples. Anil pointed out these results were achieved in partnership with NVIDIA.

And this was not the end of the story. Anil explained that the superior runtime, scheduling, and resource management delivered by IGraph resulted in significant release-to-release improvements in runtime and memory for large designs as well. These trends are summarized in the figure below.