Indeed, the use of AI in chip design is garnering quite a lot of attention these days. Forbes recently wrote, “Now, the chip industry itself has reached a stage where AI is aiding in the design of these AI chips, and it is enabling engineering teams of all sizes to compete at the relentless pace required in the semiconductor industry.” It makes sense. Chips are getting larger, especially those for burgeoning applications like AI and high-performance computing and the hyperscale data centers that host them. At 46,225mm2 with 1.2 trillion transistors and 400,000 AI-optimized cores, the Wafer-Scale Engine (WSE) from Cerebras is the biggest chip built so far. Yet, it’s becoming practically unfeasible to grow teams to scales that are needed to take on the increased workload of designing these chips, while still maintaining business sustainability.
So, AI offers a way to scale to meet design and business targets. Consider the task of digital implementation, one of the most complex stages of chip design where a great idea begins to take physical shape. Place-and-route (P&R) tools have done a remarkable job keeping up with the complexity of silicon technologies – determining where to place logic and IP blocks and how to route the traces and interconnects that connect it all. Yet the inputs to P&R constitute a vast search space of potential solutions, spanning functionality (macro-architecture), form (micro-architecture), and fit (silicon technology). Clearly, manually processing and analyzing this data can involve weeks of experimentation, with engineers forced to make complex decisions on the fly. What if AI technology can help shave off a substantial chunk of this time by taking the guesswork and manual effort out of the task? What if, with AI, you could accomplish more with your existing team?
P&R is just one example where AI can play a role. Given the increasing complexity of designs, with the vast number of iterations, corners, etc. involved, there are opportunities to optimize many other areas in the process.