Taming Advanced Node Physical Verification – Customer Perspective

Physical verification presents a particularly difficult challenge at advanced nodes. With an explosion of rules and operations, the traditional, trusted methods of yesterday no longer scale to meet new requirements. A modern software architecture that enables innovative methodologies is required. In a prior post on SemiWiki.com, this topic was discussed, along with an overview of the approach offered by the Synopsys IC Validator™ physical verification signoff solution.

In this post, we explore the results achieved with IC Validator by a leading provider of compute, networking, and storage semiconductor solutions. The company’s advanced designs move, store, process, and secure the world’s data. These results were presented at the recent Synopsys Converge event. Here are details on the company’s perspective on taming advanced-node physical verification.

The company is helping power the AI era with a comprehensive infrastructure portfolio spanning compute, connectivity, and storage.

Its physical verification CAD team provides centralized support across the company’s most advanced semiconductor products. That scope creates real challenges for very large, near-reticle-size designs, which the presentation addressed.

The presentation was organized into three primary areas:

• Early, Dirty Design Handling
• New Complex Rules Debug & Fixing
• Hardware Resource Management

Throughout the presentation, specific details about the highlighted problems were discussed, along with how IC Validator addressed them. Let’s begin.

In the first segment of the talk, the challenges of verifying immature design data were discussed. In this scenario, a “garbage in, garbage out” issue must be addressed. The team wants to minimize time spent chasing errors that will be fixed later as the design matures. The goal is to identify and fix major issues that could impact design quality or convergence as early as possible in the design cycle—especially when the design is still in an early, “dirty” stage. IC Validator’s Explorer capability was identified as particularly useful here.

For DRC checks, critical and relevant rules are selected automatically, and a violation heatmap is generated. Focusing on the most important rules reduces the noise from redundant error markers while also reducing verification runtime. The violation heatmap provides a per-rule (or combined) visual representation of error-marker density across the layout. The densest areas pinpoint major design problems that, if addressed, can quickly reduce the error count. An example is shown on the right. More traditional debug methods are often time-consuming and inefficient. Narrowing the problem to a subset of rules and a specific region of the layout saves significant debug time.

Another area of focus was the complex antenna and PERC ESD rules. For advanced-node antenna checks, the customer highlighted how challenging it can be to interpret complex foundry rules. Consequently, debugging to find root causes and deploying the best strategies to resolve violations is time-consuming. As before, close collaboration with the Synopsys IC Validator teams enabled accelerated antenna checking and enhanced error-debugging and fixing recipes.

The strategy included developing stricter antenna checks at the block level to prevent chip-level antenna violations. The teams also worked together to improve debug-rule coverage. Furthermore, it was determined that enabling the antenna debug feature had minimal impact on runtime: the feature was enabled widely, significantly assisting the debug process.

The antenna-fixing guidance provided by IC Validator was also discussed in some detail. It was explained that after antenna checking, IC Validator can provide fixing guidance for selected errors. The interface presents complex rules in a user-friendly GUI, invoked by right-clicking on an error and selecting “Antenna Fix Guidance.”

IC Validator then displays the antenna equation, the variables in the equation, and the current value of each variable. The user can solve the equation for any of the variables, displaying the range of values for that variable that will make the rule pass. The user can also experiment with “what-if” scenarios by trying out different values of the variables. This capability speeds up the review and repair process significantly. The figure below illustrates an example of usage. Synopsys also provided the customer with a “tip” that IC Validator VUE can be launched standalone, without needing to change the layout viewer, which improved the efficiency of validating fixes.

Programmable electrical rules checking (PERC) for electrostatic discharge (ESD) was discussed next. It was explained that PERC ESD violations such as Point-to-Point (P2P) and Current Density (CD) are increasingly affecting advanced-node designs. The company runs these checks on every block and at the chip level. The speed of IC Validator allowed these checks to be run for both block and full-chip scenarios.

Challenges were encountered during debugging. In this case, the iterative P2P debug cycle included reviewing the heatmap to pinpoint the layer or segment that needed repair. Re-running the entire design after every fix became quite time-consuming. Once again, close collaboration between Synopsys and the customer team addressed this problem.

After the initial PERC ESD run, the IC Validator PERC P2P debugger now allows heatmap generation for selective full paths to visualize and debug paths using a heatmap.

This P2P debugger with a heatmap runs 3× faster than a full PERC P2P run, allowing the team to perform faster iterations of debug, fix, and rerun. An overview of what the interface looks like is shown in the figure below.

The company has substantial hardware resources available for physical verification. Despite this, schedule surprises can stress any system. A year-end scenario was described in which, due to schedule changes, several large designs all needed to be completed in December. Delaying to the following year was not an option.

In this scenario, IC Validator’s Elastic Compute feature saved the day. A near-reticle-size chip would need about 17.5 hours and 20 servers to complete the run. The system’s smart scheduling feature allowed the job to begin with two available servers, and additional hardware was intelligently added as it became available. Resources were also dynamically released when they were no longer needed.

This approach saved up to 30% of hardware resources with no turnaround-time impact. A key benefit was that it was not necessary to wait 11 hours to get all the resources needed. The IC Validator run completed in time for the December tapeout. An overview of the progress achieved with dynamic hardware allocation is shown in the figure below.