As transistor dimensions shrink and the tradeoff between computing power and performance widens, emulation is becoming the modus operandi for power verification. While there is an increasing push for chip designers to build optimal designs that can reduce power consumption, it is easier said than done.
Let’s say a chip consumes 1 watt of power and you want to reduce its power consumption at the implementation level — this approach would allow for about 5-7% power reduction. However, doing that alone does not solve the problem. For greater power efficiency, identifying and reducing activity flow in the system, be it during the packet generation process or identifying redundant data in the flow, can reduce power consumption by 2x. As power continues to be a bigger piece in the silicon puzzle, this approach of leveraging multi-stage activity is witnessing growing interest from chipmakers.
How does emulation fit into the picture?
Essentially, emulation mimics the behavioral characteristics of the actual hardware, implements the design mapped, and accurately simulates the activity flow in the system. While dynamic power and peak power are a function of the streams of data flowing through the system, it is important to evaluate the average power demands of the system for accurate power profiling.
Compared to when simulation was the powerhouse for verification, emulation provides a 1000x speed up. This equips chipmakers with the ability to run realistic workloads across an exhaustive number of cycles to perform accurate diagnostics of the average power consumed and identify components where peaks are high — a critical component in power verification.
Adopting a “shift left” approach becomes imperative to ensure timely detection of power-hungry activities early in the software development life cycle (SDLC). The idea being that it is faster and more cost-effective to detect vulnerabilities and resolve power issues early on than in post-silicon. This requires fast and comprehensive verification tools to ensure teams can complete successful SoC power analysis and optimization within the tight schedule constraints of a design cycle.
The effectiveness of compiling complex designs on emulation systems depends on several factors like capacity, its ability to run in specific functional modes to determine pass or fail, and debugging capabilities. To meet with such formidable challenges, it is critical for next-gen emulation systems to leverage fast emulation hardware technologies to meet short turnaround times.