There’s no question that chip designs are getting more complex, driven by the power, performance, and area (PPA) demands of applications like artificial intelligence (AI), automotive chips, and cloud computing. This complexity, of course, trickles down to the design and testbench code. When engineers can find and fix bugs before sending their code to downstream simulation, emulation, and implementation tools, that makes the whole design process that much more efficient.
How can you generate correct-by-construction code for a more productive chip design and verification process? Let’s explore how in this blog post.
While typing a document, functions like auto-correct and spell checking make it more efficient to generate a clean copy. What if writing SystemVerilog code for your chip design was just as efficient? As hardware description and hardware verification languages go, SystemVerilog is one of the most commonly used. However, it also happens to be an extraordinarily complex language, with RTL constructs, assertions, and support for object-oriented programming and constrained-random testbenches. Designers have to fully compile and elaborate their SystemVerilog code, allowing connection of all parts of their design and testbench and also enabling complex checks.
Much like the software development process, with RTL code for chip designs, it’s best from a time and cost perspective to address bugs before they become costlier and more time-consuming to fix later in the design process. In an ideal world, designers would catch as many types of problems as they can while entering their RTL. Verification engineers would do the same while coding their testbench. When teams are able to deliver correct-by-construction code, this is much like a shift left in the software world—and in this case, the resulting productivity lift accelerates the design and verification process.