Kioxia Advances SoC Design with Cutting-Edge EDA and AI Technologies

To achieve their PPA and TAT goals, Kioxia’s Design Technology Promotion Department has identified three critical areas for improvement: accelerating feasibility studies, advancing timing Engineering Change Order (ECO) methodologies, and cost-conscious utilization of AI technologies.

1. Accelerating Feasibility Studies

SoC design often faces bottlenecks during synthesis and place-and-route (P&R) processes, largely due to the quality of input data such as RTL and floorplans. Traditional approaches could take up to a week per iteration to identify and resolve issues like routing congestion, resulting in extended development times and decreased performance, power, and area (PPA) metrics.

To address this, Kioxia has implemented Synopsys’ RTL Architect, enabling rapid physical synthesis and comprehensive analysis. By customizing the tool environment—focusing only on necessary inspection items and streamlining workflows—the company reduced execution time by 80% compared to conventional tools. This breakthrough allowed engineers to evaluate up to ten floorplan options in just one week, accelerating problem detection and feedback cycles and ultimately improving both PPA and TAT.

2. Advancing Timing ECO Methodologies

Timing ECO is the final and critical phase before tape-out in SoC development. As SoCs become larger and more complex, timing violations have increased, and design rule complexity has made fixing more challenging. Previously, Kioxia relied on PT-ECO, but the need for improved convergence led to the adoption of Synopsys’ PrimeClosure.

By collaborating with Synopsys to optimize settings and workflows, Kioxia developed a proprietary PrimeClosure environment. The result was a significant improvement in timing convergence: violations that previously required four iterations to resolve with PT-ECO could now be addressed in just two with PrimeClosure. This cut the ECO period in half and helped ensure timely tape-outs. Some challenges remain, such as unsupported placement rules and longer switching times between analysis modes, but ongoing collaboration with Synopsys aims to resolve these issues.

3. Cost-Conscious AI Utilization 

With the increasing complexity of EDA tools, optimizing flows and settings has become more time- and resource-intensive. Kioxia evaluated Synopsys’ DSO.ai (Design Space Optimization), which uses AI to autonomously explore the design space and automate tuning tasks. While DSO.ai improved PPA metrics and reduced leakage power, it also increased hardware resource costs.

 To balance cost and efficiency, Kioxia evaluated AI Fusion, a technology that leverages historical data to narrow the search space and reduce resource requirements. AI Fusion, integrated directly into Fusion Compiler™, requires minimal setup and expertise. Evaluations showed up to a 10% reduction in leakage power and an 80% cost savings compared to DSO.ai, without sacrificing design quality. Some issues with execution time and result reproducibility were addressed by using features like Warm Start and Replay, which improve consistency and reduce run times.

The combined adoption of RTL Architect, PrimeClosure, and AI Fusion technology has enabled Kioxia to streamline SoC development. Early design phases now benefit from faster feasibility studies and higher input data quality, while late phases see improved timing convergence and shorter TAT. In synthesis and P&R, AI Fusion technology part of Fusion Compilerhas demonstrated efficiency gains and significant cost reductions.

These innovations have already delivered measurable benefits in actual product development, and Kioxia is planning to accelerate future deployments. Looking ahead, the company has identified two new challenges for continued improvement: optimizing hierarchical partitioning for ever-larger circuits and refining macro configuration and placement for further PPA gains.

Kioxia’s collaboration with Synopsys remains crucial. The company expresses gratitude for the technical support received and looks forward to continued partnership in developing future methodologies and technologies.