Optimizing the RTL Design Flow with Real-Time PPA Analysis

Jim Schultz

Mar 09, 2023 / 5 min read

It’s not uncommon for register transfer level (RTL) designers to be unaware of how their chip design choices will impact power, performance, and area (PPA). But what if you could have these insights on hand early on? How would this change the way that you develop your RTL design? And what kind of impact could this have on the value of your product?

Traditionally, many RTL designers are far removed from the process of physical implementation. Once they’ve developed their module, they throw it over the wall to the implementation team for integration. It’s quite possible, however, that one particular set of algorithms or architectural approach might be better than another set of choices for the design’s PPA targets. By the time physical implementation engineers discover these impacts, it is often too late to make meaningful changes to the RTL. In addition, implementation reports offer little guidance to the RTL designer on how to improve the PPA bottlenecks.

Now, there’s a way for RTL designers to debug problems in a familiar environment and make impactful changes at the earliest stages of chip design. The integration of Synopsys RTL Architect physically aware RTL analysis, exploration, and optimization system with the market-leading Synopsys Verdi® automated debug system provides these insights in an environment that most RTL designers are very familiar with. Read on to learn more about how this tool integration gives you a new superpower.

PPA Doesn’t Have to Be an Afterthought in RTL Design

The RTL design community tends to be verification centric, with the majority of the engineers having front-end RTL and verification expertise and a minority with back-end synthesis and place-and-route expertise. RTL engineers tend to focus on building functional RTL, simulating it to ensure that the code does what it is intended to do. They have traditionally seen full synthesis as a back-end issue. PPA and coding issues are typically afterthoughts, considered late in the design cycle. Until now, RTL engineers also haven’t had a tool or methodology that could absorb PPA feedback within their RTL design toolkit.

Without a means to explore and understand the impact of the block-level RTL at the higher level (partition, sub-chip, or chip), there hasn’t been an easy way to perform fast, incremental RTL synthesis. As a result, issues aren’t detected until weeks or months later, after the RTL has been handed over to the physical chip design team for implementation. By this time, it’s often too difficult to change the design to improve PPA. Changes could break test, timing, and power constraints. Instead, it is left to the backend team to improve PPA. However, waiting until the place-and-route stage to improve PPA leads to smaller PPA gains and longer runtimes. Improving PPA during implementation is even more challenging at advanced nodes since moving cells and wires is more difficult due to the plethora of foundry rules that must be obeyed.

Another common scenario that occurs is synthesis of the RTL with wide margins. The RTL design is then taken into placement and routing, where back-end engineers must contend with over-margining and apply optimization techniques to hit their PPA requirements. However, the further down the chip design flow, the less impact any changes will make. So, this approach is not geared toward making a meaningful impact on the design, nor does it allow engineers the flexibility of positioning their products in an opportune way.

Physical-Optimized RTL Speeds Design Closure By Up to 5x, with Better PPA

The integration of RTL Architect with the Verdi platform provides RTL designers with the ability to address problems before the implementation team discovers them. This results in a bigger impact on PPA and reduces the time spent in implementation.

RTL Architect is the industry’s first physically aware RTL analysis, exploration, and optimization system with signoff technology integration. The solution uses a fast, multi-dimensional implementation prediction engine that predicts the PPA and congestion impact of RTL changes. With the integration of the Verdi system, RTL coders can now use the familiar environment to debug PPA bottlenecks. RTL Architect performs predictive synthesis and implementation behind the scenes and delivers the reports so that the RTL designer does not need a background in physical design to get results.

The workflow is as follows:

RTL Architect Verdi Integration | Synopsys

  • RTL Architect performs a fast, predictive synthesis and implementation.
  • The RTL user launches the Verdi debug environment, then reads the RTL and the PPA data from RTL Architect.
  • The Verdi system displays a high-level table with sorting/filtering mechanisms, such as worst timing-based modules, worst power, worst congestion. The metric information for timing, power, and congestion is aggregated by both hierarchy and construct/line. As such, the RTL developer can easily see information such as how much power down a particular “case” statement consumes, or the total congestion that’s caused by a particular block.
  • The RTL developer who is familiar with the Verdi environment can see PPA metrics on their RTL and make changes from this well-known setting.
  • After modifying the RTL code, the RTL designer can use RTL Architect to again analyze timing, power, and congestion.

Overall, this integration between the two solutions provides an excellent bridge between synthesis/implementation engineers and the RTL development team. The PPA database can be easily shared to provide implementation-quality metrics back to the RTL developer.

RTL Architect Verdi Bidirectional Link | Synopsys

Aside from enhanced PPA outcomes, the integration between RTL Architect and the Verdi environment also reduces the number of RTL handoffs, resulting in a 3x to 5x faster schedule than the traditional synthesis and backend chip design flow. The unified GUI workbench provides teams with a multi-layered view of the hierarchy, the layout, the cell, and the RTL code. Whether RTL designers are aiming to locate timing bottlenecks, pinpoint power problems, identify congestion caused by logic or layout, or optimize their floorplan, they can do so from their familiar Verdi environment.

For a closer look at the solution in action, check out this preview of a technical demo and register here to watch the full demo.

Learn More at SNUG Silicon Valley

You can also learn more about the integrated products from technical sessions at our upcoming SNUG Silicon Valley conference at the Santa Clara Convention Center:

  • 11:15a.m. – 12:00p.m., March 29: Synopsys RTL Architect use case model to improve RTL quality: Arteris designer experience
  • 1:30p.m. – 2:15p.m., March 30: PPA optimization using RTL Architect: Meta learnings

As competition continues to heat up in the semiconductor space, RTL designers can no longer afford to ignore the impact of their design choices on PPA. The integration of RTL Architect with the Verdi environment provides an easy way to get earlier insights into PPA issues, so these problems can be resolved for an overall better product and faster RTL closure.

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