Another consideration is the workflow efficiency and efficacy among the different teams involved in the overall design process: architecture, design, implementation, IP creation/integration, packaging, etc. For example, traditionally – in the 2DIC world – it’s a relatively simple step of passing the completed chip-level design to the packaging team. However, with 3DICs, this stage entails much more back and forth because the resulting design may not meet the much more exacting packaging requirements.
This back and forth between teams is in large part due to how the system-level optimization happens. In both the 2D and 3D IC cases, ultimately, it’s up to the chip designer to extract the design’s maximum performance at the architectural level. Now, while the level of abstraction for a traditional 2D SoC has evolved from the transistor to the IP level, with 3DICs the level of abstraction is at the chiplet level. Optimizing the design of chiplets to meet performance targets is far more challenging, especially given that these chiplets could be on different process nodes and support various functions. A complete system might include low-power-memory IP, SerDes blocks, computing matrix, and other components, and, of course, everything must work well together once stacked.
Packaging decisions should, therefore, be made based on the performance targets for the system as a whole and with consideration of factors like boundaries and connections when the dies are ultimately stacked. Maybe 2.5D packaging is ideal, or 3D, or a hybrid. As should be evident, there is a significant opportunity to smooth out the workflow between the different teams for greater productivity and quality of results.
The 3DIC architecture also highlights new technical challenges in areas like thermal management and testing. On the thermal side, the TSVs used to connect the dies can lead to poor lateral heat distribution and more heat dissipation, both of which can hamper system performance if not properly managed. From a test perspective, since testing tools can only access the bottom die, a design-for-test approach is needed to identify trouble spots along the entire stack.