Synopsys 3DIC Compiler is the electronic design automation (EDA) industry’s only unified platform for end-to-end multi-die design and integration within one package. It provides a single graphical user environment with 3D visualization, supporting the exploration, design, implementation, validation, and signoff of 3DICs. It is built on the Synopsys Fusion Design Platform™ SoC-scale IC design common data model, providing scalability in capacity and performance. 3DIC Compiler enables hundreds of thousands of inter-die interconnects, which traditional IC packaging tools cannot deliver. It offers a full set of automated features along with power integrity, as well as thermal and noise-aware optimization that minimizes the number of design iterations.
Benefits of this technology include:
- A holistic approach to multi-die integration, for an optimal system-in-a-package solution
- Powerful 3D viewing of the unified platform, providing an intuitive environment and shortening overall integration time
- Seamless integration of Ansys’ silicon-package-PCB technology for system-level signal integrity, power integrity and thermal analysis, enabling faster convergence and reducing the need for iterations
Designers are splitting SoCs into multiple dies to improve yield, PPA, and scalability for various use cases such as die splitting, die disaggregation, compute scaling and aggregation of functions. To meet the extensive die and SDRAM connectivity requirements for such multi-die SoCs, designers are using Synopsys’ silicon-proven DesignWare Die-to-Die and HBM IP solutions. The solutions offer low-latency controllers and power-efficient PHYs available on the most advanced FinFET processes, supporting 2.5D or 3D packaging technologies. The die-to-die IP enables reliable 112G XSR and parallel-based HBI links, and the HBM IP allows up to 921 GB/s HBM3 SDRAMs.