Accelerating EDA with AI for Improved SoC

Stelios Diamantidis

Jul 22, 2020 / 4 min read

The electronic design automation (EDA) industry has always had a unique symbiotic relationship with its customers. It has consistently provided the advances in chip design tools, methodologies and processes that enable the next great innovations in computing, telecommunications, automotive and a host of other industries. There would be no keeping up with Moore’s Law without EDA. But Moore’s Law has also been an enabler for EDA itself.

EDA veterans will remember the days when software tools like simulators, place and route systems and timing analysis tools moved to open “workstations” from the likes of Sun Microsystems and HP. This was a big advancement over proprietary hardware/software bundled solutions and paved the way for a new era in EDA, including one of the most seminal shifts in chip design — the ability to transform a high level design concept into an optimized and detailed description ready to be handed off for implementation – the Synopsys-invented step known as logic synthesis. That transition wouldn’t have been possible if the workstation companies themselves (and their chip suppliers) hadn’t had access to powerful design tools to begin with. They were able to run computationally intensive applications we developed in an open platform, eventually putting the power of automation in more people’s hands. That’s just one example of how this synergetic cycle works.

AI Unlocking Opportunities in EDA

Fast forward to the era of artificial intelligence; AI is one of the most talked about technologies of the current generation and holds vast potential. AI-enabled chips and sophisticated algorithms are key to many great advancements in a wide range of industries. Many of those breakthroughs have been enabled by the latest EDA innovations. As the synergetic cycle rolls forward, we are leveraging the power of AI to create new applications that design chips faster and better.

That’s why we’re excited about the DSO.aiTM technology we announced earlier this year. It stands for “design space optimization AI,” representing one of the most challenging chip design processes in the entire development flow. Specifically, searching the vast combined space of design and silicon technology choices to identify optimal recipes for the Holy Grail of chip design: performance, power and area (PPA).

In a complex chip with tens of millions of gates targeting a 5-nanometer process, the design flow is a very large space of potential solutions, nearly incalculable in human terms. Floorplan exploration alone can encompass trillions of possibilities for design teams to experiment with. And there is never a single “right” answer signifying ultimate completion.

In this environment, traditional, manual, design space exploration (DSE) can take many months of effort to reach satisfactory closure, and is strewn with tedious error-prone tasks and frustrating trial-and-error re-do cycles. By consequence, the exploration of choices in typical chip design workflows tends to be limited, and designs are rarely pushed to their architectural limits for PPA. It is a huge search problem with hundreds of millions of dollars of investment on the line.

This is where recent advancements in AI-based search technology can offer exciting ideas. New AI techniques like reinforcement learning (RL) have taught AI to play complex games like Chess or Go; synthesize and optimize neural networks; and match computational workloads to different types of accelerators. What if we could teach AI to search for optimal design recipes by using today’s tools?

Augmenting Human Expertise

We first applied AI to our back-end physical design approach — place-and-route, floor planning and associated tasks. We designed engines to ingest large data streams generated by design tools and use them to explore search spaces, observing how a design evolves over time and adjusting design choices, technology parameters and workflows to guide the exploration process toward multi-dimensional optimization objectives.

In many ways, the complexity of the chip design process is an ideal fit for the decision-making capabilities of AI algorithms. We have seen the human toll in dealing with the vastness of a modern chip design, often leading to decision fatigue and over-constraining the design. brings immediate visibility into hard-to-explore design-process-technology solution spaces. And, it means maximizing the benefits of silicon process technologies and pushing the limits of scaling.

We like to use the term “autonomous” in describing how goes about its tasks. In much the same way an autonomous vehicle learns the rules of the road and driving parameters, teaches itself the most optimal way to use design tools to meet – and in many cases exceed – targets. is not meant to replace human expertise! Quite the opposite, it is designed to augment it. With autonomous search capabilities, design teams are freed up to focus on more important things. In addition to applying deep and efficient thinking to the big challenges, they can automate less consequential decisions, like tuning tool settings or orchestrating experiments. Know-how is shared and applied across entire design teams, allowing them to consistently operate at a near-expert level. This level of productivity means that engineers are now available for more projects, can apply more time on a given problem to achieve better results, are able to handle larger parts of a project and are freed to focus on creative and value-added tasks.

Accelerating Design Velocity

Most critically in competitive markets, utilizing AI is a significant time saver. The productivity increases design teams are seeing are beyond impressive. Our early development partners have seen disruptive results in the throughput they can achieve.

How disruptive? Across four initial design projects, we were able to get to results an average of 86% faster than existing design flows, and use fewer staff to do it. In addition, all the projects met or exceeded the PPA requirements.

AI Silicon Design | Synopsys

One of our development partners, Samsung Electronics, noted, “ was able to achieve these results in as few as 3 days; a process that typically takes multiple experts over a month of experimentation.”

At the moment our focus with is on physical design; however, the entire chip design workflow is ripe for AI-based optimization, which can help teams get more competitive products to market faster. With today’s hypercompetitive markets and stringent silicon manufacturing requirements, the difference between a good recipe and an optimal recipe can be 100s of MHz of performance, hours of battery life and millions of dollars in design costs.

Continue Reading