How Parasitic Extraction Can Make or Break Your High-speed Chip Design

With the ever-growing need for faster, smaller, and smarter devices to keep our world going, it’s hard not to wonder how engineers are keeping up. First, there was 4G, then 5G, and now 6G is on the horizon — not to mention smarter phones, TVs, and watches, which all run on those high-speed networks, as well as artificial intelligence (AI) and the expectations that come with high-speed digital technology. The complexity of these advancements is evident through the extensive design efforts that go into the internal components of our most beloved devices.

Design teams are increasingly seeking new, advanced tools to help them lower costs and remediate issues that can lead to missed deadlines and suboptimal products. The ability to accurately simulate all aspects of designs before manufacturing has proven to be a game-changer in the fast-paced world of semiconductor development.

Within all electronic devices lies at least one, but typically multiple integrated circuits (IC) — commonly called chips — made from silicon, a semiconductor material. This chip is where small electronic components called transistors are formed within the silicon and then wired together with interconnects layered on top of the silicon surface. ICs can take three to four months to manufacture, and they cannot be repaired or altered in the event of an error. So, if a chip comes back from the manufacturer and doesn’t work properly, there is a great deal of time and money lost. Therefore, a design must be exhaustively tested before manufacturing. Ansys multiphysics simulations deliver a comprehensive solution to IC design with an unparalleled range of physical modeling capabilities. These simulations make it possible to model complex, simultaneous interactions between multiple physics domains that strongly impact an IC's performance.

Parasitics and the Need for High Speed

Just how many things can go wrong in the design of an IC? Unfortunately, as design speeds increase, the opportunity for error also increases. This is the price engineers must pay when designing chips capable of managing today’s high-frequency communication technologies. High-speed designs are very sensitive to unwanted, unintended effects, known as parasitics, which can be difficult to diagnose. Often too late, issues can arise that affect the structural, physical, thermal, or electromagnetic properties of an IC. The growing size of designs and novel and complex physical interactions within advanced features like photonics and three-dimensional integrated circuits (3D-IC) make these diagnoses even more difficult.

When combined with tight deadlines, engineers are under more pressure than ever before. Ansys simulation can help make IC development and testing a more manageable task by quickly analyzing root causes and drastically cutting down time and cost.

Just how common are parasitics, and how are they located? Parasitics can be found in all semiconductor designs and usually consist of two fundamental concepts: resistance and capacitance (RC). These exist in circuit design due to the inescapable physics of a layout and the materials of the design. Parasitics can cause signal delay, power loss, and signal fidelity degradation.

The problematic aspect of designing to prevent parasitics is how difficult it can be to pinpoint an issue's exact cause and location. The Synopsys ParagonX integrated circuit design analysis and debugging tool takes the guesswork out of interconnect parasitics by giving graphical feedback and sophisticated analyses that help locate parasitics within selected signals in a design, avoiding the need to simulate the entire design.

With high-speed chips operating at frequencies of several gigahertz or beyond, there is an increased requirement to consider inductance (L) parasitics as well. Mutual inductance and self-inductance are additional pain points for engineers, as well as electromagnetic effects such as coupling and crosstalk, which result from higher frequencies and speeds. As our devices and the components within them get smaller, parasitic impacts only increase. For example, distortion of the signals that travel along signal buses, or signal lines, delay and degrade overall communication between components largely due to parasitics.

Inductance is a nonlocal effect that can be difficult to diagnose as it impacts components and their surrounding elements, and it only becomes more intense as frequencies and electromagnetic fields increase. Therefore, these phenomena need to be modeled with even higher accuracy.

As our devices and the components within them get smaller, there is less room for error — quite literally. Spreading components further apart to avoid crosstalk and coupling would be an ideal resolution, but one that is expensive and problematic when space is limited. Shielding these electromagnetically sensitive components is another option, but it is also costly to implement. So, how can engineers pinpoint the issues that will arise before an IC design is finalized and manufactured?

The electromagnetic (EM) solver enables users to design with an awareness of these electromagnetic parasitics. When employed early, this solver can help users find issues sooner rather than later in the design cycle, when a late fix could cause serious delays. By locating electromagnetic issues that are not otherwise intuitively evident and are too complex for hand calculations, this solver brings critical precision to the IC design process.