Hyper-Convergent Chip Designs: News & Trends

Synopsys Editorial Staff

Dec 15, 2021 / 2 min read

Most everyone in the semiconductor industry has heard of Moore’s law, the observation of Gordon Moore, Intel Corporation’s founder, that the number of transistors in ICs doubles roughly every couple of years. But today, we’ve packed in just about as many transistors as physically possible with traditional design methods, and Moore’s law is slowing. What’s next?

Thinking about chip design differently, on a systemic level, you open up new possibilities to achieve greater performance, power, and area (PPA) benefits that surpass those of generations past. Approaching the matter systemically is about hyperconvergence—bringing together a variety of technologies into one advanced package, enabling 3DICs and more. Foundational to this new, systemic thinking comes integration techniques and tools for hyper-convergent design flows that will deliver a unified analysis of the complex systems contained in these chips, helping to make these designs more practical, efficient, and cost effective to produce.

Central Computer Processor digital concept

To help you stay on top of the latest news and trends on hyper-convergent designs, here are five insightful articles from our experts:

Mike Gianfagna welcomes us to the SysMoore era of chip design—where scale and systemic complexity converge into a new class of semiconductors. Learn about this new era of semiconductor design and why your EDA tools play a critical role.

Raja Tabet and Anand Thiruvengadam take a close look at hyperconvergence in semiconductor design, and why this trend is redefining how we perform circuit simulation.

Tom Hsieh demonstrates how PrimeSim Continuum is foundational for a “multi-discipline verification methodology, providing a common license, use model, and input and output syntax for the first time.”

Kenneth Larson describes why vertical dimension requires a rethinking of your IC design strategy and the ideal platform to achieve optimal PPA per cubic mm.

Shekhar Kapoor walks you through the challenges inherent in 3DIC designs and explains why point tools addressing subsets of these complex challenges fall short. A unified platform to tackle design convergence challenges in multi-die chips is the way of the future.

We are now in the SysMoore era, defined by scale and systemic complexity to provide a way forward for semiconductor innovation. This, in turn, calls for a hyper-convergent design flow to achieve greater efficiency, along with time and cost savings that would otherwise be prohibitive. As our experts have explained, EDA solutions are rising to the occasion to meet the demands of this new world of innovation.

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